Power analysis of embedded software: a first step towards software power minimization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low-power design
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ISCA '99 Proceedings of the 26th annual international symposium on Computer architecture
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Proceedings of the 37th Annual Design Automation Conference
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Proceedings of the 37th Annual Design Automation Conference
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DATE '00 Proceedings of the conference on Design, automation and test in Europe
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Proceedings of the 38th annual Design Automation Conference
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ICCD '98 Proceedings of the International Conference on Computer Design
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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Proceedings of the 41st annual Design Automation Conference
Hybrid simulation for embedded software energy estimation
Proceedings of the 42nd annual Design Automation Conference
Dynamic phase analysis for cycle-close trace generation
CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Efficiently exploring architectural design spaces via predictive modeling
Proceedings of the 12th international conference on Architectural support for programming languages and operating systems
Efficient architectural design space exploration via predictive modeling
ACM Transactions on Architecture and Code Optimization (TACO)
Architecture performance prediction using evolutionary artificial neural networks
Evo'08 Proceedings of the 2008 conference on Applications of evolutionary computing
Execution characteristics of embedded applications on a Pentium 4-based personal computer
Journal of Embedded Computing
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This paper presents a novel approach for an efficient, yet accurate estimation technique for power consumption and performance of embedded and general purpose applications. Our approach is adaptive in nature and is based on detecting sections of code characterized by high temporal locality (also called hotspots) in the execution profile of the benchmark being executed on a target processor. The technique itself is architecture and input independent and can be used for both embedded, as well as for general purpose processors. We have implemented a hybrid simulation engine which can significantly shorten the simulation time by using on-the-fly profiling for critical sections of the code and by reusing this information during power/performance estimation for the rest of the code. By using this strategy, we were able to achieve up to 20X better accuracy compared to a flat, non-adaptive sampling scheme and a simulation speed-up of up to 11.84X with a maximum error of 1.03% for performance and 1.92% for total energy on a wide variety of media and general purpose applications.