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The paper presents a novel strategy aimed at modeling the instruction energy consumption of 32-bits microprocessors. The proposed instruction-level pow er model is founded on afunctional decomposition of the activities accomplished by a generic microprocessor and exhibits significant generalization capabilities. It allo ws estimation of the pow er figures of the en tire instruction-set starting from the analysis of a subset, as w ell as to po w er characterize new processors using the model obtained by considering other microprocessors.