Static timing analysis of embedded software
DAC '97 Proceedings of the 34th annual Design Automation Conference
Software timing analysis using HW/SW cosimulation and instruction set simulator
Proceedings of the 6th international workshop on Hardware/software codesign
Computer architecture (2nd ed.): a quantitative approach
Computer architecture (2nd ed.): a quantitative approach
An instruction-level functionally-based energy estimation model for 32-bits microprocessors
Proceedings of the 37th Annual Design Automation Conference
Static timing analysis of embedded software on advanced processor architectures
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Retargetable static timing analysis for embedded software
Proceedings of the 14th international symposium on Systems synthesis
Advanced Computer Architectures
Advanced Computer Architectures
Fast Simulation of Computer Architectures
Fast Simulation of Computer Architectures
Measuring Experimental Error in Microprocessor Simulation
ISCA '01 Proceedings of the 28th annual international symposium on Computer architecture
An assembly-level execution-time model for pipelined architectures
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Computer
Asim: A Performance Model Framework
Computer
Compilation-based software performance estimation for system level design
HLDVT '00 Proceedings of the IEEE International High-Level Validation and Test Workshop (HLDVT'00)
Affinity-Driven System Design Exploration for Heterogeneous Multiprocessor SoC
IEEE Transactions on Computers
Performance modeling of embedded applications with zero architectural knowledge
CODES/ISSS '10 Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
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This paper proposes an original model of the execution time of assembly instructions in superscalar architectures. The approach is based on a rigorous mathematical model and provides a methodology and a toolset to perform data analysis and model tuning. The methodology also provides a framework for building new trace simulators for generic architectures. The results obtained show a good accuracy paired with a satisfactory computational efficiency.