Power analysis of a 32-bit embedded microcontroller
ASP-DAC '95 Proceedings of the 1995 Asia and South Pacific Design Automation Conference
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Power analysis and minimization techniques for embedded DSP software
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
The SimpleScalar tool set, version 2.0
ACM SIGARCH Computer Architecture News
The design and use of simplepower: a cycle-accurate energy estimation tool
Proceedings of the 37th Annual Design Automation Conference
An instruction-level functionally-based energy estimation model for 32-bits microprocessors
Proceedings of the 37th Annual Design Automation Conference
A codesign virtual machine for hierarchical, balanced hardware/software system modeling
Proceedings of the 37th Annual Design Automation Conference
Function-level power estimation methodology for microprocessors
Proceedings of the 37th Annual Design Automation Conference
Wattch: a framework for architectural-level power analysis and optimizations
Proceedings of the 27th annual international symposium on Computer architecture
A static power estimation methodolodgy for IP-based design
Proceedings of the conference on Design, automation and test in Europe
Energy estimation and optimization of embedded VLIW processors based on instruction clustering
Proceedings of the 39th annual Design Automation Conference
Cosimulation-based power estimation for system-on-chip design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A D&T Roundtable: Are Single-Chip Multiprocessors in Reach?
IEEE Design & Test
How Many System Architectures?
Computer
Schedulers as model-based design elements in programmable heterogeneous multiprocessors
Proceedings of the 40th annual Design Automation Conference
Instruction Level Power Analysis and Optimization of Software
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
PowerScope: A Tool for Profiling the Energy Usage of Mobile Applications
WMCSA '99 Proceedings of the Second IEEE Workshop on Mobile Computer Systems and Applications
Software Power Estimation and Optimization for High Performance, 32-bit Embedded Processors
ICCD '98 Proceedings of the International Conference on Computer Design
Power Savings in Embedded Processors through Decode Filer Cache
Proceedings of the conference on Design, automation and test in Europe
EAC: A Compiler Framework for High-Level Energy Estimation and Optimization
Proceedings of the conference on Design, automation and test in Europe
Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Modeling Shared Resource Contention Using a Hybrid Simulation/Analytical Approach
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Microarchitectural power modeling techniques for deep sub-micron microprocessors
Proceedings of the 2004 international symposium on Low power electronics and design
Layered, Multi-Threaded, High-Level Performance Design
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Benchmark-Based Design Strategies for Single Chip Heterogeneous Multiprocessors
CODES+ISSS '04 Proceedings of the international conference on Hardware/Software Codesign and System Synthesis: 2004
MinneSPEC: A New SPEC Benchmark Workload for Simulation-Based Computer Architecture Research
IEEE Computer Architecture Letters
MiBench: A free, commercially representative embedded benchmark suite
WWC '01 Proceedings of the Workload Characterization, 2001. WWC-4. 2001 IEEE International Workshop
High-level power modeling, estimation, and optimization
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Scenario-Oriented Design for Single Chip Heterogeneous Multiprocesso
IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 10 - Volume 11
High-level power analysis for multi-core chips
CASES '06 Proceedings of the 2006 international conference on Compilers, architecture and synthesis for embedded systems
Interrupt modeling for efficient high-level scheduler design space exploration
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Webpage-based benchmarks for mobile device design
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Holistic design and caching in mobile computing
CODES+ISSS '08 Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis
Power optimization for application-specific networks-on-chips: A topology-based approach
Microprocessors & Microsystems
Instructions and hardware designs for accelerating SNOW 3G on a software-defined radio platform
Analog Integrated Circuits and Signal Processing
Collecting signatures to model latency tolerance in high-level simulations of microthreaded cores
Proceedings of the 2012 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools
Design of energy-efficient, adaptable throughput systems at near/sub-threshold voltage
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special section on adaptive power management for energy and temperature-aware computing systems
Contextual partitioning for speech recognition
ACM Transactions on Embedded Computing Systems (TECS)
Power consumption of 3D networks-on-chips: Modeling and optimization
Microprocessors & Microsystems
Hi-index | 14.98 |
Single chip heterogeneous multiprocessors (SCHMs) are becoming more commonplace, especially in portable devices where reduced energy consumption is a priority. The use of coordinated collections of processors which are simpler or which execute at lower clock frequencies is widely recognized as a means of reducing power while maintaining latency and throughput. A primary limitation of using this approach to reduce power at the system level has been the time to develop and simulate models of many processors at the instruction set simulator level. High-level models, simulators, and design strategies for SCHMs are required to enable designers to think in terms of collections of cooperating, heterogeneous processors in order to reduce power. Toward this end, this paper has two contributions. The first is to extend a unique, preexisting high-level performance simulator, the Modeling Environment for Software and Hardware (MESH), to include power annotations. MESH can be thought of as a thread-level simulator instead of an instruction-level simulator. Thus, the problem is to understand how power might be calibrated and annotated with program fragments instead of at the instruction level. Program fragments are finer-grained than threads and coarser-grained than instructions. Our experimentation found that compilers produce instruction patterns that allow power to be annotated at this level using a single number over all compiler-generated fragments executing on a processor. Since energy is power*time, this makes system runtime (i.e., performance) the dominant factor to be dynamically calculated at this level of simulation. The second contribution arises from the observation that high-level modeling is most beneficial when it opens up new possibilities for organizing designs. Thus, we introduce a design strategy, enabled by the high-level performance power-simulation, which we refer to as spatial voltage scaling. The strategy both reduces overall system power consumption and improves performance in our example. The design space for this design strategy could not be explored without high-level SCHM power-performance simulation.