Reuse: What's Wrong with This Picture?
IEEE Software
Schedulers as model-based design elements in programmable heterogeneous multiprocessors
Proceedings of the 40th annual Design Automation Conference
Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Modeling Shared Resource Contention Using a Hybrid Simulation/Analytical Approach
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Benchmark-based design strategies for single chip heterogeneous multiprocessors
Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Layered, Multi-Threaded, High-Level Performance Design
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Power-Performance Simulation and Design Strategies for Single-Chip Heterogeneous Multiprocessors
IEEE Transactions on Computers
System-level design: orthogonalization of concerns and platform-based design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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The design of next generation single chip computers may require the selection, programming and coordination of tens to hundreds of individual processing elements (PEs) of several or tens of heterogeneous types. This paper outlines differences in the design process for these next generation single chip systems from that of traditional designs. Then it focuses on a novel design strategy, Scenario-Oriented Design (SOD). SOD is just one design strategy that arises because of the potential of considering applications, schedulers, and hardware as they interact to form a system instead of viewing them as separate design domains. By leveraging one against the other, the system and its design process can be optimized in new ways. This is made possible by reducing the modeling detail of each design domain within a system in high level simulation.