Models and languages for parallel computation
ACM Computing Surveys (CSUR)
Automatic generation of embedded memory wrapper for multiprocessor SoC
Proceedings of the 39th annual Design Automation Conference
A D&T Roundtable: Are Single-Chip Multiprocessors in Reach?
IEEE Design & Test
Codesign-extended applications
Proceedings of the tenth international symposium on Hardware/software codesign
Event Model Interfaces for Heterogeneous System Analysis
Proceedings of the conference on Design, automation and test in Europe
Layered, Multi-Threaded, High-Level Performance Design
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Modeling Shared Resource Contention Using a Hybrid Simulation/Analytical Approach
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Scenario-Oriented Design for Single Chip Heterogeneous Multiprocesso
IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 10 - Volume 11
Power-Performance Simulation and Design Strategies for Single-Chip Heterogeneous Multiprocessors
IEEE Transactions on Computers
High-level modeling and simulation of single-chip programmable heterogeneous multiprocessors
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Scheduler implementation in MP SoC design
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Interrupt modeling for efficient high-level scheduler design space exploration
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Amdahl's law revisited for single chip systems
International Journal of Parallel Programming
Memory subsystem simulation in software TLM/T models
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
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As System On a Chip (SoC) designs become more like Programmable Heterogeneous Multiprocessors (PHMs), the highest levels of design will place emphasis on the custom design of elements that were traditionally associated with systems in the large. We motivate how schedulers that make dynamic, data-dependent decisions at run-time will be key design elements in PHM SoCs. Starting from a fundamental model, the role schedulers play in PHMs is developed. Model-based scheduling is introduced as an approach to designing schedulers that optimize a PHM's performance. Due to the complexity of the PHM design space, convergence on optimal design requires high-level modeling and simulation. In model-based scheduling, high-level models of scheduling decisions result in actual design elements that appear in real systems. Experiments for a simple two-processor PHM that does a mix of image and text compression are included. Results show the effectiveness of model-based scheduling.