Scalable high speed IP routing lookups
SIGCOMM '97 Proceedings of the ACM SIGCOMM '97 conference on Applications, technologies, architectures, and protocols for computer communication
Models and languages for parallel computation
ACM Computing Surveys (CSUR)
Computer architecture (2nd ed.): a quantitative approach
Computer architecture (2nd ed.): a quantitative approach
The structure of the “THE”-multiprogramming system
Communications of the ACM
Performance specification of software components
SSR '01 Proceedings of the 2001 symposium on Software reusability: putting software reuse in context
Automatic generation of embedded memory wrapper for multiprocessor SoC
Proceedings of the 39th annual Design Automation Conference
Theory of Modeling and Simulation
Theory of Modeling and Simulation
A D&T Roundtable: Are Single-Chip Multiprocessors in Reach?
IEEE Design & Test
Colif: A Design Representation for Application-Specific Multiprocessor SOCs
IEEE Design & Test
Reuse: What's Wrong with This Picture?
IEEE Software
How Many System Architectures?
Computer
Codesign-extended applications
Proceedings of the tenth international symposium on Hardware/software codesign
The design context of concurrent computation systems
Proceedings of the tenth international symposium on Hardware/software codesign
Schedulers as model-based design elements in programmable heterogeneous multiprocessors
Proceedings of the 40th annual Design Automation Conference
FORGE: A Framework for Optimization of Distributed Embedded Systems Software
IPDPS '03 Proceedings of the 17th International Symposium on Parallel and Distributed Processing
Event Model Interfaces for Heterogeneous System Analysis
Proceedings of the conference on Design, automation and test in Europe
A Layered, Codesign Virtual Machine Approach to Modeling Computer Systems
Proceedings of the conference on Design, automation and test in Europe
Modeling Shared Resource Contention Using a Hybrid Simulation/Analytical Approach
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Layered, Multi-Threaded, High-Level Performance Design
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
A framework for comparing models of computation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
System-level design: orthogonalization of concerns and platform-based design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Interrupt modeling for efficient high-level scheduler design space exploration
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Source-level timing annotation and simulation for a heterogeneous multiprocessor
Proceedings of the conference on Design, automation and test in Europe
EURASIP Journal on Embedded Systems - C-Based Design of Heterogeneous Embedded Systems
A platform-based design framework for joint SW/HW multiprocessor systems design
Journal of Systems Architecture: the EUROMICRO Journal
Fast and accurate processor models for efficient MPSoC design
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Journal of Signal Processing Systems
Delivering real-time behaviour
Domain modeling and the duration calculus
Automatic workload generation for system-level exploration based on modified GCC compiler
Proceedings of the Conference on Design, Automation and Test in Europe
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
Collecting signatures to model latency tolerance in high-level simulations of microthreaded cores
Proceedings of the 2012 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools
Application Workload Modelling via Run-Time Performance Statistics
International Journal of Embedded and Real-Time Communication Systems
Early-phase performance exploration of embedded systems with ABSOLUT framework
Journal of Systems Architecture: the EUROMICRO Journal
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Heterogeneous multiprocessing is the future of chip design with the potential for tens to hundreds of programmable elements on single chips within the next several years. These chips will have heterogeneous, programmable hardware elements that lead to different execution times for the same software executing on different resources as well as a mix of desktop-style and embedded-style software. They will also have a layer of programming across multiple programmable elements forming the basis of a new kind of programmable system which we refer to as a Programmable Heterogeneous Multiprocessor (PHM). Current modeling approaches use instruction set simulation for performance modeling, but this will become far too prohibitive in terms of simulation time for these larger designs. The fundamental question is what the next higher level of design will be. The high-level modeling, simulation and design required for these programmable systems poses unique challenges, representing a break from traditional hardware design. Programmable systems, including layered concurrent software executing via schedulers on concurrent hardware, are not characterizable with traditional component-based hierarchical composition approaches, including discrete event simulation. We describe the foundations of our layered approach to modeling and performance simulation of PHMs, showing an example design space of a network processor explored using our simulation approach.