Model composition for scheduling analysis in platform design
Proceedings of the 39th annual Design Automation Conference
Transformation of SDL specifications for system-level timing analysis
Proceedings of the tenth international symposium on Hardware/software codesign
Schedulers as model-based design elements in programmable heterogeneous multiprocessors
Proceedings of the 40th annual Design Automation Conference
Proceedings of the 40th annual Design Automation Conference
Scheduling Analysis Integration for Heterogeneous Multiprocessor SoC
RTSS '03 Proceedings of the 24th IEEE International Real-Time Systems Symposium
A General Framework for Analysing System Properties in Platform-Based Embedded System Designs
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Layered, Multi-Threaded, High-Level Performance Design
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Formal Methods for Integration of Automotive Software
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe: Designers' Forum - Volume 2
Interval-based analysis in embedded system design
Mathematics and Computers in Simulation - Special issue: Selected papers from the 4th IMACS symposium on mathematical modelling (4th MATHMOD)
Java event broadcasting in CSCW environment
Proceedings of the 3rd international symposium on Principles and practice of programming in Java
High-level modeling and simulation of single-chip programmable heterogeneous multiprocessors
ACM Transactions on Design Automation of Electronic Systems (TODAES)
How OEMs and suppliers can face the network integration challenges
Proceedings of the conference on Design, automation and test in Europe: Designers' forum
Improved offset-analysis using multiple timing-references
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Buffer space optimisation with communication synthesis and traffic shaping for NoCs
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Performance analysis of multimedia applications using correlated streams
Proceedings of the conference on Design, automation and test in Europe
Analysis and optimisation of hierarchically scheduled multiprocessor embedded systems
International Journal of Parallel Programming - Special Issue on Multiprocessor-based embedded systems
Intra- and inter-processor hybrid performance modeling for MPSoC architectures
CODES+ISSS '08 Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis
Cache-aware timing analysis of streaming applications
Real-Time Systems
Minimizing CPU energy in real-time systems with discrete speed management
ACM Transactions on Embedded Computing Systems (TECS)
A recursive approach to end-to-end path latency computation in heterogeneous multiprocessor systems
CODES+ISSS '09 Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Scenario extraction for a refined timing-analysis of automotive network topologies
Proceedings of the Conference on Design, Automation and Test in Europe
Learning early-stage platform dimensioning from late-stage timing verification
Proceedings of the Conference on Design, Automation and Test in Europe
On buffering with stochastic guarantees in resource-constrained media players
CODES+ISSS '11 Proceedings of the seventh IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Combining network calculus and scheduling theory to improve delay bounds
Proceedings of the 20th International Conference on Real-Time and Network Systems
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Complex embedded systems consist of hardware and softwarecomponents from different domains, such as control and signalprocessing, many of them supplied by different IP vendors. Theembedded system designer faces the challenge to integrate, optimizeand verify the resulting heterogeneous systems. While formalverification is available for some subproblems, the analysisof the whole system is currently limited to simulation or emulation.In this paper, we tackle the analysis of global resource sharing,scheduling, and buffer sizing in heterogeneous embedded systems.For many practically used preemptive and non-preemptivehardware and software scheduling algorithms of processors andbusses, semi-formal analysis techniques are known. However, theycannot be used in system level analysis due to incompatibilities oftheir underlying event models. This paper presents a technique tocouple the analysis of local scheduling strategies via an event interfacemodel. We derive transformation rules between the mostimportant event models and provide proofs where necessary. Weuse expressive examples to illustrate their application.