Multiprocessor priority ceiling based protocols
Multiprocessor priority ceiling based protocols
Scheduling Algorithms for Multiprogramming in a Hard-Real-Time Environment
Journal of the ACM (JACM)
Synchronization in Real-Time Systems: A Priority Inheritance Approach
Synchronization in Real-Time Systems: A Priority Inheritance Approach
Schedulability Analysis for Tasks with Static and Dynamic Offsets
RTSS '98 Proceedings of the IEEE Real-Time Systems Symposium
Event Model Interfaces for Heterogeneous System Analysis
Proceedings of the conference on Design, automation and test in Europe
Trading End-to-End Latency for Composability
RTSS '05 Proceedings of the 26th IEEE International Real-Time Systems Symposium
A Formal Approach to Multi-Dimensional Sensitivity Analysis of Embedded Real-Time Systems
ECRTS '06 Proceedings of the 18th Euromicro Conference on Real-Time Systems
Semantics-Preserving Design of Embedded Control Software from Synchronous Models
IEEE Transactions on Software Engineering
Reliable performance analysis of a multicore multithreaded system-on-chip
CODES+ISSS '08 Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis
On the Scalability of Real-Time Scheduling Algorithms on Multicore Platforms: A Case Study
RTSS '08 Proceedings of the 2008 Real-Time Systems Symposium
Proceedings of the Conference on Design, Automation and Test in Europe
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Today's innovations in the automotive sector are, to a great extent, based on electronics. The increasing integration complexity and stringent cost reduction goals turn E/E platform design into a challenging task. Timing/performance is becoming a key aspect of architecture design, because the platform must be dimensioned to provide just the right amount of computing power and network bandwidth, including reserves for future extensions, in order to be cost efficient. In other words, it must be as powerful as needed but as cheap as possible. Finding this sweet spot is a key challenge. Therefore, OEMs and Tier-1 are in search of new methods, processes, and timing analysis techniques that assist in early platform design stages. In this paper, we demonstrate how some selected techniques that are established for verification (in late design stages) can also be used to guide the design (in early stages). We present examples in the areas ECU (OSEK), buses (CAN, FlexRay) and gated networks. Flow and applicability aspects are highlighted. As a key result, we show that and how we can learn from late-stage verification for early-stage design. Finally, we also outline future challenges in the area of multi-core ECUs.