Transformation of SDL specifications for system-level timing analysis

  • Authors:
  • Marek Jersak;Kai Richter;Rafik Henia;Rolf Ernst;Frank Slomka

  • Affiliations:
  • Technical University of Braunschweig, D-38106 Braunschweig, Germany;Technical University of Braunschweig, D-38106 Braunschweig, Germany;Technical University of Braunschweig, D-38106 Braunschweig, Germany;Technical University of Braunschweig, D-38106 Braunschweig, Germany;University of Paderborn, D-33098 Paderborn, Germany

  • Venue:
  • Proceedings of the tenth international symposium on Hardware/software codesign
  • Year:
  • 2002

Quantified Score

Hi-index 0.00

Visualization

Abstract

Complex embedded systems are typically specified using multiple domain-specific languages. After code-generation, the implementation is simulated and tested. Validation of non-functional properties, in particular timing, remains a problem because full test coverage cannot be achieved for realistic designs. The alternative, formal timing analysis, requires a system representation based on key application and architecture properties. These properties must first be extracted from a system specification to enable analysis. In this paper we present a suitable transformation of SDL specifications for system-level timing analysis. We show ways to vary modeling accuracy in order to apply available formal techniques. A practical approach utilizing a recently developed system model is presented.