COSYN: hardware-software co-synthesis of embedded systems
DAC '97 Proceedings of the 34th annual Design Automation Conference
Combining multiple models of computation for scheduling and allocation
Proceedings of the 6th international workshop on Hardware/software codesign
Representation of process mode correlation for scheduling
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Intervals in software execution cost analysis
ISSS '00 Proceedings of the 13th international symposium on System synthesis
XML Bible
RATAN: A Tool for Rate Analysis and Rate Constraint Debugging for Embedded Systems
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Hardware/Software Codesign of Embedded Systems -The SPI Workbench
WVLSI '99 Proceedings of the IEEE Computer Society Workshop on VLSI'99
Specification and analysis of timing constraints for embedded systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Hierarchical finite state machines with multiple concurrency models
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
SPI: a system model for heterogeneously specified embedded systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Transformation of SDL specifications for system-level timing analysis
Proceedings of the tenth international symposium on Hardware/software codesign
Model-based development of in-vehicle software
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Machine-assisted proof support for validation beyond Simulink
ICFEM'07 Proceedings of the formal engineering methods 9th international conference on Formal methods and software engineering
Applying timed interval calculus to simulink diagrams
ICFEM'06 Proceedings of the 8th international conference on Formal Methods and Software Engineering
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Time-driven simulation models typically model timing in an idealized way that is over-constrained and cannot be directly implemented. In this paper we present a transformation to relax the constraints imposed by a time-driven simulation model, thus creating a larger design space. We transform the system into SPI, a common intermediate representation for heterogeneously specified embedded systems. At the SPI level critical timing constraints are (re)introduced, resulting in a representation that is well suited for global system analysis, optimization and synthesis.