VHDL generation from SDL specifications
CHDL'97 Proceedings of the IFIP TC10 WG10.5 international conference on Hardware description languages and their applications : specification, modelling, verification and synthesis of microelectronic systems: specification, modelling, verification and synthesis of microelectronic systems
Resource sharing in hierarchical synthesis
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Proceedings of the 6th international workshop on Hardware/software codesign
Hardware/software co-design of an ATM network interface card: a case study
Proceedings of the 6th international workshop on Hardware/software codesign
ISSS '00 Proceedings of the 13th international symposium on System synthesis
Hardware/Software Codesign and Rapid Prototyping of Embedded Systems
IEEE Design & Test
Euro-Par '96 Proceedings of the Second International Euro-Par Conference on Parallel Processing-Volume II
Integrating SDL and VHDL for System-Level Hardware Design
CHDL '93 Proceedings of the 11th IFIP WG10.2 International Conference sponsored by IFIP WG10.2 and in cooperation with IEEE COMPSOC on Computer Hardware Description Languages and their Applications
Semi-automated Design of High-Performance Communication Subsystems
HICSS '98 Proceedings of the Thirty-First Annual Hawaii International Conference on System Sciences - Volume 3
Mixed Abstraction Level Hardware Synthesis from SDL for Rapid Prototyping
RSP '99 Proceedings of the Tenth IEEE International Workshop on Rapid System Prototyping
RSP '00 Proceedings of the 11th IEEE International Workshop on Rapid System Prototyping (RSP 2000)
A General Approach for the Specification of Real-Time Systems with SDL
SDL '01 Proceedings of the 10th International SDL Forum Copenhagen on Meeting UML
Transformation of SDL specifications for system-level timing analysis
Proceedings of the tenth international symposium on Hardware/software codesign
Hardware synthesis from coarse-grained dataflow specification for fast HW/SW cosynthesis
Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Optimized RTL Code Generation from Coarse-Grain Dataflow Specification for Fast HW/SW Cosynthesis
Journal of Signal Processing Systems
Integrating RTL IPs into TLM designs through automatic transactor generation
Proceedings of the conference on Design, automation and test in Europe
Automatic customization of device drivers for IP-cores used with assorted CPU organizations
CODES+ISSS '09 Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Correct-by-construction generation of device drivers based on RTL testbenches
Proceedings of the Conference on Design, Automation and Test in Europe
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A new approach for the translation of SDL specifications to a mixed hardware/software system is presented. Based on the computational model of communicating extended finite state machines (EFSM) the control flow is separated from data flow of the SDL process. Hence for the first time it is possible to generate a mixed hardware/software implementation of an SDL process. This technique also reduces the complexity for high-level and register-transfer synthesis tools for the hardware parts of the system. The advantage of this methodology is shown by a design example of a wireless communication chip.