Interfacing incompatible protocols using interface process generation
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Automatic generation of functional vectors using the extended finite state machine model
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Automatic synthesis of interfaces between incompatible protocols
DAC '98 Proceedings of the 35th annual Design Automation Conference
Generating mixing hardware/software systems from SDL specifications
Proceedings of the ninth international symposium on Hardware/software codesign
System Design with SystemC
Synthesizing Converters Between Finite State Protocols
ICCD '91 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Convertibility verification and converter synthesis: two faces of the same coin
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Verification of Transaction-Level SystemC models using RTL Testbenches
MEMOCODE '03 Proceedings of the First ACM and IEEE International Conference on Formal Methods and Models for Co-Design
Transaction level modeling: an overview
Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Maintaining consistency between systemC and RTL system designs
Proceedings of the 43rd annual Design Automation Conference
Introduction to Automata Theory, Languages, and Computation (3rd Edition)
Introduction to Automata Theory, Languages, and Computation (3rd Edition)
Hybrid, Incremental Assertion-Based Verification for TLM Design Flows
IEEE Design & Test
The temporal logic of programs
SFCS '77 Proceedings of the 18th Annual Symposium on Foundations of Computer Science
Specification, Synthesis, and Simulation of Transactor Processes
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Automatic customization of device drivers for IP-cores used with assorted CPU organizations
CODES+ISSS '09 Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Correct-by-construction generation of device drivers based on RTL testbenches
Proceedings of the Conference on Design, Automation and Test in Europe
HIFsuite: tools for HDL code conversion and manipulation
EURASIP Journal on Embedded Systems
Automated construction of a cycle-approximate transaction level model of a memory controller
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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Transaction Level Modeling (TLM) is an emerging design practice for overcoming increasing design complexity. It aims at simplifying the design flow of embedded systems by designing and verifying a system at different abstraction levels. In this context, transactors play a fundamental role since they allow communication between the system components, implemented at different abstraction levels. Reuse of RTL IPs into TLM systems is a meaningful example of key advantage guaranteed by exploiting transactors. Nevertheless, transactors implementation is still manual, tedious and error-prone, and the effort spent to verify their correctness often overcomes the benefits of the TLM-based design flow. In this paper we present a methodology to automatically generate transactors for RTL IPs. We show how the transactor code can be automatically generated by exploiting the testbench of any RTL IP.