Automatic functional test generation using the extended finite state machine model
DAC '93 Proceedings of the 30th international Design Automation Conference
From VHDL Register Transfer Level to SystemC Transaction Level Modeling: A Comparative Case Study
SBCCI '03 Proceedings of the 16th symposium on Integrated circuits and systems design
Transaction level modeling: an overview
Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Integrating RTL IPs into TLM designs through automatic transactor generation
Proceedings of the conference on Design, automation and test in Europe
SystemC: From the Ground Up, Second Edition
SystemC: From the Ground Up, Second Edition
ISPA '10 Proceedings of the International Symposium on Parallel and Distributed Processing with Applications
Automatic Abstraction of RTL IPs into Equivalent TLM Descriptions
IEEE Transactions on Computers
Transaction level modeling in practice: motivation and introduction
Proceedings of the International Conference on Computer-Aided Design
| Hi-index | 0.00 |
Transaction level (TL) models are key to early design exploration, performance estimation and virtual prototyping. Their speed and accuracy enable early and rapid System-on-Chip (SoC) design evaluation and software development. Most devices have only register transfer level (RTL) models that are too complex for SoC simulation. Abstracting these models to TL ones, however, is a challenging task, especially when the RTL description is too obscure or not accessible. This work presents a methodology for automatically creating a TL model of an RTL memory controller component. The device is treated as a black box and a multitude of simulations is used to obtain results, showing its timing behavior. The results are classified into conditional probability distributions, which are reused within a TL model to approximate the RTL timing behavior. The presented method is very fast and highly accurate. The resulting TL model executes approximately 1200 times faster, with a maximum measured average timing offset error of 7.66%.