HERMES: an infrastructure for low area overhead packet-switching networks on chip
Integration, the VLSI Journal - Special issue: Networks on chip and reconfigurable fabrics
A framework for the design, synthesis and cycle-accurate simulation of multiprocessor networks
Journal of Parallel and Distributed Computing - Special issue: Design and performance of networks for super-, cluster-, and grid-computing: Part I
A systematic IP and bus subsystem modeling for platform-based system design
Proceedings of the conference on Design, automation and test in Europe: Proceedings
System-platforms-based SystemC TLM design of image processing chains for embedded applications
EURASIP Journal on Embedded Systems
A cycle-accurate transaction level SystemC model for a serial communication bus
Computers and Electrical Engineering
A reconfigurable platform for evaluating the performance of QoS networks
Journal of Systems Architecture: the EUROMICRO Journal
Automated construction of a cycle-approximate transaction level model of a memory controller
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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Transaction level (TL) modeling is regarded today as the next step in the direction of complex integrated circuits and systems design entry. This means that as this modeling level definition evolves, automated synthesis tools will increasingly support it, allowing design capture to start at a higher abstraction level than today. This work presents a comparison of traditional register transfer level (RTL) modeling and transaction level modeling through the implementation of a simple processor case study. SystemC is a language that naturally supports hardware transaction level descriptions. The R8 processor was described in SystemC TL and RTL versions and these were compared to an equivalent hand-coded VHDL RTL description in some key points, such as simulation efficiency and implementation results. The experiments indicate that TL descriptions present a faster path to system validation and that it is possible toenvisage the automation of the design flow from this level of abstraction without significant impact on the quality of the final implementation.