Verification and management of a multimillion-gate embedded core design
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
LOTTERYBUS: a new high-performance communication architecture for system-on-chip designs
Proceedings of the 38th annual Design Automation Conference
CoCo: a hardware/software platform for rapid prototyping of code compression technologies
Proceedings of the 40th annual Design Automation Conference
Verification of Transaction-Level SystemC models using RTL Testbenches
MEMOCODE '03 Proceedings of the First ACM and IEEE International Conference on Formal Methods and Models for Co-Design
From VHDL Register Transfer Level to SystemC Transaction Level Modeling: A Comparative Case Study
SBCCI '03 Proceedings of the 16th symposium on Integrated circuits and systems design
Transaction level modeling: an overview
Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Extending the transaction level modeling approach for fast communication architecture exploration
Proceedings of the 41st annual Design Automation Conference
Proceedings of the 41st annual Design Automation Conference
Platform based design: does it answer the entire SoC challenge?
Proceedings of the 41st annual Design Automation Conference
Benefits and challenges for platform-based design
Proceedings of the 41st annual Design Automation Conference
System design for DSP applications in transaction level modeling paradigm
Proceedings of the 41st annual Design Automation Conference
Transaction-Level Models for AMBA Bus Architecture Using SystemC 2.0
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe: Designers' Forum - Volume 2
A Mixed Abstraction Level Co-Simulation Case Study Using SystemC for System on Chip Verification
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe: Designers' Forum - Volume 2
SystemC-VHDL Co-Simulation and Synthesis in the HW Domain
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe: Designers' Forum - Volume 2
Exploring SW Performance Using SoC Transaction-Level Modeling
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe: Designers' Forum - Volume 2
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe: Designers' Forum - Volume 2
A Practical Approach for Bus Architecture Optimization at Transaction Level
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe: Designers' Forum - Volume 2
On-Chip Communication Architectures: System on Chip Interconnect
On-Chip Communication Architectures: System on Chip Interconnect
Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
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The topic on platform-based system modeling has received a great deal of attention today. One of the important tasks that significantly affect the effectiveness and efficiency of the system modeling is the modeling of IP components and communication between IPs. To be effective, it is generally accepted that the system modeling should be performed in two steps; In the first step, a fast but some inaccurate system modeling is considered to facilitate the simultaneous development of software and hardware. The second step then refines the models of the software and hardware blocks (i.e., IPs) to increase the simulation accuracy for the system performance analysis. Here, one critical factor required for a successful system modeling is a systematic modeling of the IP blocks and bus subsystem connecting the IPs. In this respect, this work addresses the problem of systematic modeling of the IPs and bus subsystem in different levels of refinements. In the experiments, we found that by applying our proposed IP and bus modeling methods to the MPEG-4 application, we are able to achieve 4x performance improvement and at the same time, reduce the software development time by 35%, compared to that by conventional modeling methods.