DAC '96 Proceedings of the 33rd annual Design Automation Conference
CoWare—a design environment for heterogenous hardware/software systems
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
System Design with SystemC
System-on-a-Chip: Design and Test
System-on-a-Chip: Design and Test
SystemC
Synthesis of Embedded SystemC Design: A Case Study of Digital Neural Networks
Proceedings of the conference on Design, automation and test in Europe - Volume 3
A systematic IP and bus subsystem modeling for platform-based system design
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Tackling an abstraction gap: co-simulating SystemC DE with bluespec ESL
Proceedings of the conference on Design, automation and test in Europe
Novel methodology for functional modeling and simulation of wireless embedded systems
EURASIP Journal on Embedded Systems - C-Based Design of Heterogeneous Embedded Systems
SystemC-based HW/SW co-simulation platform for system-on-chip (SoC) design space exploration
International Journal of Information and Communication Technology
Co-simulation framework of SystemC SoC virtual prototype and custom logic (abstract only)
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
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This paper focuses on co-simulation scenarios and their applications as a part of a system-on-chip (SoC) modeling and design methodology developed at Alcatel Microelectronics (now part of STMicroelectronics) within a wireless local area network (LAN) SoC project. This methodology proposes to build a SystemC-based executable model of the system to maintain a bridge between the algorithmic and the implementation worlds. The model is used in later phases by means of co-simulation of SystemC, HDL and firmware. SystemC-HDL co-simulation scenario provides a way of checking inter-operability of a single designed HW module with the SystemC model. The SystemC-Instruction Set Simulator (ISS) co-simulation provides a platform to develop and verify the firmware that will run on the selected processor core even before the HW modules are designed. It will be shown that, with sufficient tool support, these design stages reduce the complexity of the SoC design and improve the debugging capabilities.