Heterogeneous Simulation—Mixing Discrete-Event Models with Dataflow
Journal of VLSI Signal Processing Systems - Special issue on the rapid prototyping of application specific signal processors (RASSP) program
Hardware Synthesis from Term Rewriting Systems
VLSI '99 Proceedings of the IFIP TC10/WG10.5 Tenth International Conference on Very Large Scale Integration: Systems on a Chip
Modular scheduling of guarded atomic actions
Proceedings of the 41st annual Design Automation Conference
A Mixed Abstraction Level Co-Simulation Case Study Using SystemC for System on Chip Verification
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe: Designers' Forum - Volume 2
Hardware synthesis from guarded atomic actions with performance specifications
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Transaction-Level Modeling with Systemc: Tlm Concepts and Applications for Embedded Systems
Transaction-Level Modeling with Systemc: Tlm Concepts and Applications for Embedded Systems
Synthesis of synchronous assertions with guarded atomic actions
MEMOCODE '05 Proceedings of the 2nd ACM/IEEE International Conference on Formal Methods and Models for Co-Design
Automatic synthesis of cache-coherence protocol processors using Bluespec
MEMOCODE '05 Proceedings of the 2nd ACM/IEEE International Conference on Formal Methods and Models for Co-Design
Hierarchical finite state machines with multiple concurrency models
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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The growing SystemC community for system level design exploration is a result of SystemC's capability of modeling at RTL and above RTL abstraction levels. However, managing shared state concurrency using multi-threading in large SystemC models is error prone. A recent extension of SystemC called Bluespec-SystemC (BS-ESL) counters this difficulty with its model of computation employing atomic rule-based specifications. However, for simulating a model that is partly designed in SystemC and partly using BS-ESL, an interoperability semantics and implementation of such a semantics is required. This paper views the interoperability problem as an abstraction gap closure problem. To illustrate the problem, we formalize the simulation semantics of BS-ESL and discrete-event simulation of RTL SystemC and provide a solution based on this formalization.