Reliable estimation of execution time of embedded software
Proceedings of the conference on Design, automation and test in Europe
An Approach for Quantitative Analysis of Application-Specific Dataflow Architectures
ASAP '97 Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures and Processors
Zipper VDSL: a solution for robust duplex communication over telephone lines
IEEE Communications Magazine
Programmable implementations of xDSL transceiver systems
IEEE Communications Magazine
System-level design: orthogonalization of concerns and platform-based design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A systematic IP and bus subsystem modeling for platform-based system design
Proceedings of the conference on Design, automation and test in Europe: Proceedings
CODES+ISSS '06 Proceedings of the 4th international conference on Hardware/software codesign and system synthesis
On-Chip Communication Architectures: System on Chip Interconnect
On-Chip Communication Architectures: System on Chip Interconnect
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In this paper a high-level SoC architecture exploration of DMT (Discrete Multitone) VDSL transceivers (Very high speed Digital Subscriber Line) is presented. A flexible and complete virtual platform was developed for the purpose, exploiting the paradigm of "orthogonalization of concerns" (functionality independent from architecture) in the framework of Cadence VCC system level design tool. An accurate processor model, obtained through the back-annotation of profiling results on a target DSP core, allowed the exploration of different HW/SW partitioning and the study of the computational units required. A transaction-accurate VCC bus model was developed for the investigation of the on-chip bus architecture and its relevant parameters dimensioning.