Hardware/software co-simulation
DAC '94 Proceedings of the 31st annual Design Automation Conference
A methodology for accurate performance evaluation in architecture exploration
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Proceedings of the conference on Design, automation and test in Europe
Methodology for hardware/software co-verification in C/C++ (short paper)
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
A universal technique for fast and flexible instruction-set architecture simulation
Proceedings of the 39th annual Design Automation Conference
Miami: a hardware software co-simulation environment
RSP '96 Proceedings of the 7th IEEE International Workshop on Rapid System Prototyping (RSP '96)
Proceedings of the conference on Design, automation and test in Europe - Volume 1
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe: Designers' Forum - Volume 2
RTK-Spec TRON: A Simulation Model of an ITRON Based RTOS Kernel in SystemC
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Using TLM for Exploring Bus-based SoC Communication Architectures
ASAP '05 Proceedings of the 2005 IEEE International Conference on Application-Specific Systems, Architecture Processors
Automatic generation of hardware dependent software for MPSoCs from abstract system specifications
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Architecture exploration of NAND flash-based multimedia card
Proceedings of the conference on Design, automation and test in Europe
FEMU: a firmware-based emulation framework for SoC verification
CODES/ISSS '10 Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Speeding up SoC virtual platform simulation by data-dependency-aware synchronization and scheduling
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
System-level development of embedded software
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
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Virtual platform (ViP), or ESL (Electronic System Level) simulation model, is one of the most widely renowned system level design techniques. In this paper, we present a case study of creating and applying the ViP in the development of a new hard disk system called Hybrid-HDD that is one of the main features in the Windows VISTA (R). First, we summarize how we developed the ViP including the levels of timing accuracy of models, automatic generation of models from RTL code, external subsystem models, etc. Then, we explain how we exploited the ViP in software optimization. Compared with the conventional flow of software development, e.g. based on the real board, the ViP gives a better profiling capability thereby allowing designers to find more chances of code optimization. Based on the simulation and analysis with the ViP, the software optimization could improve system performance by more than 50%. However, in our case study, we found that the current ViP technique needs further improvements to become a true ESL design technique.