Virtual synchronization for fast distributed cosimulation of dataflow task graphs
Proceedings of the 15th international symposium on System Synthesis
Transaction level modeling: an overview
Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Trace-driven HW/SW cosimulation using virtual synchronization technique
Proceedings of the 42nd annual Design Automation Conference
Proceedings of the conference on Design, automation and test in Europe: Proceedings
CODES+ISSS '06 Proceedings of the 4th international conference on Hardware/software codesign and system synthesis
Fast and accurate transaction level models using result oriented modeling
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Communication architecture simulation on the virtual synchronization framework
SAMOS'07 Proceedings of the 7th international conference on Embedded computer systems: architectures, modeling, and simulation
ESL Design and Verification: A Prescription for Electronic System Level Methodology
ESL Design and Verification: A Prescription for Electronic System Level Methodology
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In this paper, we proposed a novel simulation scheme, called data-dependency-aware synchronization and scheduling, for SoC virtual platform simulation. In contrast to the conventional clock-or transaction-based synchronization, our simulation scheme can work with the clock decoupling and direct-data-access techniques to implement the trace-driven virtual synchronization methodology. In addition, we further extend the virtual synchronization concept to handle the interrupt signals in the system. This enables the porting of operating system (uCLinux) in our virtual platform. The experimental results show that our virtual platform can achieve 3 to 5 million-instructions-per-second simulation speed, or 44 times speed-up over the conventional cycle accurate approach, while still maintaining the same cycle-count accuracy.