SystemCSV - an extension of SystemC for mixed multi-level communication modeling and interface-based system design

A novel synthesis technique for communication controller hardware from declarative data communication protocol specifications

Proceedings of the 39th annual Design Automation Conference

Validation in a component-based design flow for multicore SoCs

Proceedings of the 15th international symposium on System Synthesis

System-level abstraction semantics

Proceedings of the 15th international symposium on System Synthesis

Automatic Synthesis of Communication Controller Hardware from Protocol Specifications

IEEE Design & Test

References

SystemC

System-level communication modeling for network-on-chip synthesis

Proceedings of the 2005 Asia and South Pacific Design Automation Conference

Quantitative analysis of transaction level models for the AMBA bus

Proceedings of the conference on Design, automation and test in Europe: Proceedings

TRAIN: a virtual transaction layer architecture for TLM-based HW/SW codesign of synthesizable MPSoC

Proceedings of the conference on Design, automation and test in Europe: Proceedings

Accurate yet fast modeling of real-time communication

CODES+ISSS '06 Proceedings of the 4th international conference on Hardware/software codesign and system synthesis

Creation and utilization of a virtual platform for embedded software optimization:: an industrial case study

CODES+ISSS '06 Proceedings of the 4th international conference on Hardware/software codesign and system synthesis

Fast and accurate transaction level models using result oriented modeling

Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design

Quantitative analysis of the speed/accuracy trade-off in transaction level modeling

ACM Transactions on Embedded Computing Systems (TECS)

Towards a synthesis semantics for systemC channels

CODES/ISSS '10 Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis