Proceedings of the conference on Design, automation and test in Europe
System Design with SystemC
The Integration of SystemC and Hardware-Assisted Verification
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
Automatic communication refinement for system level design
Proceedings of the 40th annual Design Automation Conference
A modular simulation framework for architectural exploration of on-chip interconnection networks
Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Transaction level modeling: an overview
Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Communication Analysis for System-On-Chip Design
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Extending the transaction level modeling approach for fast communication architecture exploration
Proceedings of the 41st annual Design Automation Conference
Systematic Transaction Level Modeling of Embedded Systems with SystemC
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Virtual Hardware Prototyping through Timed Hardware-Software Co-Simulation
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
System-level communication modeling for network-on-chip synthesis
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
System-on-chip environment: a SpecC-based framework for heterogeneous MPSoC design
EURASIP Journal on Embedded Systems - C-Based Design of Heterogeneous Embedded Systems
| Hi-index | 0.00 |
Our concept of a virtual transaction layer (VTL) architecture allows to directly map transaction-level communication channels onto a synthesizable multiprocessor SoC implementation. The VTL is above the physical MPSoC communication architecture, acting as a hardware abstraction layer for both HW and SW components. TLM channels are represented by virtual channels which efficiently route transactions between SW and HW entities through the on-chip communication network with respect to quality-of-service and realtime requirements. The goal is to methodically simplify MPSoC design by systematic HW/SW interface abstraction, thus enabling early SW verification, rapid prototyping and fast exploration of critical design issues. With TRAIN, we present our implementation of such a VTL architecture for Virtex-II Pro and PowerPC and illustrate its efficiency by experimentation.