Systematic Transaction Level Modeling of Embedded Systems with SystemC

Authors:
Wolfgang Klingauf
Affiliations:
Technical University of Braunschweig, Germany
Venue:
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Year:
2005

Citing 3
Cited 4

Transaction level modeling: an overview

Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Extending the transaction level modeling approach for fast communication architecture exploration

Proceedings of the 41st annual Design Automation Conference
Systemic Embedded Software Generation from SystemC

DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1

TRAIN: a virtual transaction layer architecture for TLM-based HW/SW codesign of synthesizable MPSoC

Proceedings of the conference on Design, automation and test in Europe: Proceedings
On-Chip Communication Architectures: System on Chip Interconnect

On-Chip Communication Architectures: System on Chip Interconnect
Generation of embedded hardware/software from systemC

EURASIP Journal on Embedded Systems
A high-throughput, high-accuracy system-level simulation framework for system on chips

VLSI Design

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Abstract

This paper gives an overview of a transaction level modeling (TLM) design flow for straightforward embedded system design with SystemC. The goal is to systematically develop both application-specific HW and SW components of an embedded system using the TLM approach, thus allowing for fast communication architecture exploration, rapid prototyping and early embedded SW development. To this end, we specify the lightweight transaction-based communication protocol SHIP and present a methodology for automatic mapping of the communication part of a system to a given architecture, including HW/SW interfaces.