DAC '97 Proceedings of the 34th annual Design Automation Conference
Mixed-level cosimulation for fine gradual refinement of communication in SoC design
Proceedings of the conference on Design, automation and test in Europe
System Design with SystemC
Quick-Turnaround ASIC Design in VHDL: Core-Based Behavioral Synthesis
Quick-Turnaround ASIC Design in VHDL: Core-Based Behavioral Synthesis
StepNP: A System-Level Exploration Platform for Network Processors
IEEE Design & Test
AMBA: Enabling Reusable On-Chip Designs
IEEE Micro
A hierarchical modeling framework for on-chip communication architectures
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Observable Time Windows: Verifying the Results of High-Level Synthesis
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Transaction-Level Models for AMBA Bus Architecture Using SystemC 2.0
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe: Designers' Forum - Volume 2
A Practical Approach for Bus Architecture Optimization at Transaction Level
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe: Designers' Forum - Volume 2
System-level design: orthogonalization of concerns and platform-based design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Fast exploration of bus-based on-chip communication architectures
Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Systematic Transaction Level Modeling of Embedded Systems with SystemC
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
A Network Traffic Generator Model for Fast Network-on-Chip Simulation
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Floorplan-aware automated synthesis of bus-based communication architectures
Proceedings of the 42nd annual Design Automation Conference
Constraint-driven bus matrix synthesis for MPSoC
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Automated throughput-driven synthesis of bus-based communication architectures
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Exploiting TLM and object introspection for system-level simulation
Proceedings of the conference on Design, automation and test in Europe: Proceedings
A systematic IP and bus subsystem modeling for platform-based system design
Proceedings of the conference on Design, automation and test in Europe: Proceedings
TRAIN: a virtual transaction layer architecture for TLM-based HW/SW codesign of synthesizable MPSoC
Proceedings of the conference on Design, automation and test in Europe: Proceedings
FABSYN: floorplan-aware bus architecture synthesis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
TLM/network design space exploration for networked embedded systems
CODES+ISSS '06 Proceedings of the 4th international conference on Hardware/software codesign and system synthesis
Automatic generation of transaction level models for rapid design space exploration
CODES+ISSS '06 Proceedings of the 4th international conference on Hardware/software codesign and system synthesis
Formal performance evaluation of AMBA-based system-on-chip designs
EMSOFT '06 Proceedings of the 6th ACM & IEEE International conference on Embedded software
On-Chip Communication Architectures: System on Chip Interconnect
On-Chip Communication Architectures: System on Chip Interconnect
CATS: cycle accurate transaction-driven simulation with multiple processor simulators
Proceedings of the conference on Design, automation and test in Europe
Modeling and simulation alternatives for the design of networked embedded systems
Proceedings of the conference on Design, automation and test in Europe
Shared resource access attributes for high-level contention models
Proceedings of the 44th annual Design Automation Conference
Event-based re-training of statistical contention models for heterogeneous multiprocessors
CODES+ISSS '07 Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Fast exploration of bus-based communication architectures at the CCATB abstraction
ACM Transactions on Embedded Computing Systems (TECS)
System-level PVT variation-aware power exploration of on-chip communication architectures
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Automated architecture synthesis for parallel programs on FPGA multiprocessor systems
Microprocessors & Microsystems
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Slotless module-based reconfiguration of embedded FPGAs
ACM Transactions on Embedded Computing Systems (TECS)
Cycle count accurate memory modeling in system level design
CODES+ISSS '09 Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Exploring serial vertical interconnects for 3D ICs
Proceedings of the 46th Annual Design Automation Conference
An automatic ABV methodology enabling PSL assertions across SLD flow for SOCs modeled in SystemC
Computers and Electrical Engineering
International Journal of Reconfigurable Computing - Special issue on selected papers from ReConFig 2008
Fast and accurate protocol specific bus modeling using TLM 2.0
Proceedings of the Conference on Design, Automation and Test in Europe
Combined system synthesis and communication architecture exploration for MPSoCs
Proceedings of the Conference on Design, Automation and Test in Europe
Evaluating carbon nanotube global interconnects for chip multiprocessor applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
The Lotterybus on-chip communication architecture
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A non-intrusive timing synchronization interface for hardware-assisted HW/SW co-simulation
Proceedings of the 49th Annual Design Automation Conference
A cycle-count-accurate simulation platform with enhanced design exploration capability
Proceedings of the 5th International ICST Conference on Simulation Tools and Techniques
Automatic generation of high-speed accurate TLM models for out-of-order pipelined bus
ACM Transactions on Embedded Computing Systems (TECS) - Special Section on ESTIMedia'10
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System-on-Chip (SoC) designs are increasingly becoming more complex. Efficient on-chip communication architectures are critical for achieving desired performance in these systems. System designers typically use Bus Cycle Accurate (BCA) models written in high level languages such as C/C++ to explore the communication design space. These models capture all of the bus signals and strictly maintain cycle accuracy, which is useful for reliable performance exploration but results in slow simulation speeds for complex designs, even when they are modeled using high level languages. Recently there have been several efforts to use the Transaction Level Modeling (TLM) paradigm for improving simulation performance in BCA models. However these BCA models capture a lot of details that can be eliminated when exploring communication architectures.In this paper we extend the TLM approach and propose a new and faster transaction-based modeling abstraction level (CCATB) to explore the communication design space. Our abstraction level bridges the gap between the TLM and BCA levels, and yields an average performance speedup of 55 over BCA models. We demonstrate how fast and accurate exploration of tradeoffs is possible for high-performance shared bus architectures such as AMBA 2.0 and AMBA 3.0 (AXI) in industrial strength designs at the proposed abstraction level.