Design of Silicon IP Cores for Biorthogonal Wavelet Transforms
Journal of VLSI Signal Processing Systems - Special issue on signal processing systems design and implementation
Deterministic Built-in Pattern Generation for Sequential Circuits
Journal of Electronic Testing: Theory and Applications
Interface Design for Core-Based Systems
IEEE Design & Test
19.1 Built-In Self Testing of Sequential Circuits Using Precomputed Test Sets
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
Extending the transaction level modeling approach for fast communication architecture exploration
Proceedings of the 41st annual Design Automation Conference
Fast exploration of bus-based on-chip communication architectures
Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Fast exploration of bus-based communication architectures at the CCATB abstraction
ACM Transactions on Embedded Computing Systems (TECS)
| Hi-index | 0.00 |
From the Publisher:Application-specific standard products (ASSPs) and application-specific integrated circuits (ASICs) are expected to become more than fifty percent of the $10 billion VLSI Digital Signal Processing (DSP) market in year 2000. With rapidly shrinking time-to-market (TTM) requirements, and multiple design goals that seek to optimize sample rate, clock speed, area, and power, the novel core-based behavioral synthesis methodology presented in this book shows how organizations can meet these new challenges effectively and consistently over the next decade. The authors show how VLSI chips can be rapidly designed within a VHDL-based synthesis environment using a pre-designed library of core components. The core library represents synthesizable units of behavior (function and control) that are both application-specific and organization-specific, empowering the chip designer with a competitive advantage. The key to the quick-turnaround is the high amount of systematic reuse utilized within the design methodology. The percolation of accurate power, speed, area, and timing information to higher levels of abstraction allows rapid and efficient exploration of the design space facilitating the optimization of these objectives individually or concurrently. System integration and test of ASICs into board-level designs is also facilitated. Quick-Turnaround ASIC Design with VHDL: Core-Based Behavioral Synthesis presents a new approach to behavioral synthesis that uses a pre-designed library of DSP cores, providing a highly competitive alternative to existing high-level synthesis tools for DSP.