Executing temporal logic programs
Executing temporal logic programs
A Test Design Methodology for Protocol Testing
IEEE Transactions on Software Engineering
Quick-Turnaround ASIC Design in VHDL: Core-Based Behavioral Synthesis
Quick-Turnaround ASIC Design in VHDL: Core-Based Behavioral Synthesis
Seven More Myths of Formal Methods
IEEE Software
An Algorithm for Exact Bounds on the Time Separation of Events in Concurrent Systems
IEEE Transactions on Computers
Techniques for reducing read latency of core bus wrappers
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Prefetching for improved bus wrapper performance in cores
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Formal Verification of Reconfigurable Cores
FCCM '99 Proceedings of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Pre-Fetching for Improved Core Interfacing
Proceedings of the 12th international symposium on System synthesis
Bandwidth tracing arbitration algorithm for mixed-clock SoC with dynamic priority adaptation
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
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Current chips and "systems-on-chips" (SOCs) consist of a number of interacting library components (or cores) expressed in VHDL, Verilog, or other HDLs. Simulation-based HDLs, intended for capturing low-level functionality and timing, may not be ideal for a design methodology that includes inter-component communication protocol design (e.g., deadlock, starvation), architecture selection, integration and test, where timing abstraction and the capability to include real-time dependencies may be the preferred goals. Formal methods may be utilized at the system level to study the abstracted temporal and functional interactions between various RTL (and other) cores (whose actual structure and behavior can be hidden) as part of the design methodology. We describe the role of temporal abstraction in system-on-chip design, and describe its benefits vis-a-vis traditional approaches. Our methodology allows inclusion of of new and legacy components that can be both electronic and mechanical in nature.