Pre-Fetching for Improved Core Interfacing

Authors:
Roman Lysecky;Frank Vahid;Tony Givargis;Rilesh Patel
Affiliations:
Department of Computer Science and Engineering, University of California, Riverside;Department of Computer Science and Engineering, University of California, Riverside;Department of Computer Science and Engineering, University of California, Riverside;Department of Computer Science and Engineering, University of California, Riverside
Venue:
Proceedings of the 12th international symposium on System synthesis
Year:
1999

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Abstract

Reuse of cores can reduce design time for systems-on-a-chip. Such reuse is dependent on being able to easily interface a core to any bus. To enable such interfacing, many propose separating a core's interface from its internals. However, this separation can lead to a performance penalty when reading a core's internal registers. We introduce pre-fetching, which is analogous to caching, as a technique to reduce or eliminate this performance penalty, involving a tradeoff with power and size. We describe the pre-fetching technique, classify different types of registers, describe our initial pre-fetching architectures and heuristics for certain classes of registers, and highlight experiments demonstrating the performance improvements and size/power tradeoffs.