The Chinook hardware/software co-synthesis system
ISSS '95 Proceedings of the 8th international symposium on System synthesis
Communication synthesis for distributed embedded systems
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
CoWare—a design environment for heterogenous hardware/software systems
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
Generation of interconnect topologies for communication synthesis
Proceedings of the conference on Design, automation and test in Europe
Proceedings of the 37th Annual Design Automation Conference
Fast performance analysis of bus-based system-on-chip communication architectures
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Techniques for reducing read latency of core bus wrappers
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Proceedings of the conference on Design, automation and test in Europe
On-chip communication architecture for OC-768 network processors
Proceedings of the 38th annual Design Automation Conference
Traffic analysis for on-chip networks design of multimedia applications
Proceedings of the 39th annual Design Automation Conference
Efficient exploration of the SoC communication architecture design space
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Pre-Fetching for Improved Core Interfacing
Proceedings of the 12th international symposium on System synthesis
SystemC
A modular simulation framework for architectural exploration of on-chip interconnection networks
Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
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Layout Conscious Bus Architecture Synthesis for Deep Submicron Systems on Chip
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Analyzing On-Chip Communication in a MPSoC Environment
Proceedings of the conference on Design, automation and test in Europe - Volume 2
On-chip traffic modeling and synthesis for MPEG-2 video applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Scheduling and Timing Analysis of HW/SW On-Chip Communication in MP SoC Design
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe: Designers' Forum - Volume 2
An Application-Specific Design Methodology for STbus Crossbar Generation
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Floorplan-aware automated synthesis of bus-based communication architectures
Proceedings of the 42nd annual Design Automation Conference
SBCCI '05 Proceedings of the 18th annual symposium on Integrated circuits and system design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Constraint-driven bus matrix synthesis for MPSoC
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Automated throughput-driven synthesis of bus-based communication architectures
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Application specific NoC design
Proceedings of the conference on Design, automation and test in Europe: Proceedings
COSMECA: application specific co-synthesis of memory and communication architectures for MPSoC
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Statistical on-chip communication bus synthesis and voltage scaling under timing yield constraint
Proceedings of the 43rd annual Design Automation Conference
CODES+ISSS '06 Proceedings of the 4th international conference on Hardware/software codesign and system synthesis
System-level power-performance trade-offs in bus matrix communication architecture synthesis
CODES+ISSS '06 Proceedings of the 4th international conference on Hardware/software codesign and system synthesis
On-Chip Communication Architectures: System on Chip Interconnect
On-Chip Communication Architectures: System on Chip Interconnect
Early wire characterization for predictable network-on-chip global interconnects
Proceedings of the 2007 international workshop on System level interconnect prediction
Designing application-specific networks on chips with floorplan information
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
NoC Design and Implementation in 65nm Technology
NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
Proceedings of the 44th annual Design Automation Conference
Arbiter synthesis approach for SoC multi-processor systems
Computers and Electrical Engineering
Robust on-chip bus architecture synthesis for MPSoCs under random tasks arrival
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Run-time integration of reconfigurable video processing systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Slack allocation based co-synthesis and optimization of bus and memory architectures for MPSoCs
Proceedings of the conference on Design, automation and test in Europe
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
SAMBA-bus: A high performance bus architecture for system-on-chips
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Embedded Systems Design
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In this article, we present an approach to automatic generation of communication topologies for statically scheduled systems of subsystems. Given a specification containing a set of processes that communicate via abstract send and receive functions, we show how a cost-efficient communication topology consisting of one or more buses without arbitration scheme can be set up for such applications.