Fundamentals of queueing theory (2nd ed.).
Fundamentals of queueing theory (2nd ed.).
DAC '97 Proceedings of the 34th annual Design Automation Conference
High-speed policy-based packet forwarding using efficient multi-dimensional range matching
Proceedings of the ACM SIGCOMM '98 conference on Applications, technologies, architectures, and protocols for computer communication
Communication synthesis for distributed embedded systems
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Bus-based communication synthesis on system level
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Proceedings of the 37th Annual Design Automation Conference
Efficient exploration of the SoC communication architecture design space
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
AMBA: Enabling Reusable On-Chip Designs
IEEE Micro
The Sun Fireplane Interconnect
IEEE Micro
Evaluation of the Traffic-Performance Characteristics of System-on-Chip Communication Architectures
VLSID '01 Proceedings of the The 14th International Conference on VLSI Design (VLSID '01)
Beyond best effort: router architectures for the differentiated services of tomorrow's Internet
IEEE Communications Magazine
Proceedings of the conference on Design, automation and test in Europe - Volume 2
×pipesCompiler: A Tool for Instantiating Application Specific Networks on Chip
Proceedings of the conference on Design, automation and test in Europe - Volume 2
TheoSim: combining symbolic simulation and theorem proving for hardware verification
SBCCI '04 Proceedings of the 17th symposium on Integrated circuits and system design
ParIS: a parameterizable interconnect switch for networks-on-chip
SBCCI '04 Proceedings of the 17th symposium on Integrated circuits and system design
HERMES: an infrastructure for low area overhead packet-switching networks on chip
Integration, the VLSI Journal - Special issue: Networks on chip and reconfigurable fabrics
Performance Evaluation and Design Trade-Offs for Network-on-Chip Interconnect Architectures
IEEE Transactions on Computers
Design, Synthesis, and Test of Networks on Chips
IEEE Design & Test
An event-based monitoring service for networks on chip
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A flexible framework for communication evaluation in SoC design
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
A survey of research and practices of Network-on-chip
ACM Computing Surveys (CSUR)
A design methodology for application-specific networks-on-chip
ACM Transactions on Embedded Computing Systems (TECS)
On-Chip Communication Architectures: System on Chip Interconnect
On-Chip Communication Architectures: System on Chip Interconnect
Towards a formal theory of on chip communications in the ACL2 logic
ACL2 '06 Proceedings of the sixth international workshop on the ACL2 theorem prover and its applications
A Generic Model for Formally Verifying NoC Communication Architectures: A Case Study
NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
An evolutionary approach to collective communication scheduling
Proceedings of the 9th annual conference on Genetic and evolutionary computation
Router architecture for high-performance NoCs
Proceedings of the 20th annual conference on Integrated circuits and systems design
A predictive NoC architecture for vision systems dedicated to image analysis
EURASIP Journal on Embedded Systems
Mesh-of-tree deterministic routing for network-on-chip architecture
Proceedings of the 18th ACM Great Lakes symposium on VLSI
A monitoring-aware network-on-chip design flow
Journal of Systems Architecture: the EUROMICRO Journal
An evolutionary design technique for collective communications on optimal diameter-degree networks
Proceedings of the 10th annual conference on Genetic and evolutionary computation
Multicast parallel pipeline router architecture for network-on-chip
Proceedings of the conference on Design, automation and test in Europe
Executable formal specification and validation of NoC communication infrastructures
Proceedings of the 21st annual symposium on Integrated circuits and system design
CuNoC: A dynamic scalable communication structure for dynamically reconfigurable FPGAs
Microprocessors & Microsystems
Dynamically configurable bus topologies for high-performance on-chip communication
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A flexible framework for communication evaluation in SoC design
International Journal of Parallel Programming
Evolutionary optimization of multistage interconnection networks performance
Proceedings of the 11th Annual conference on Genetic and evolutionary computation
Power optimization for application-specific networks-on-chips: A topology-based approach
Microprocessors & Microsystems
Evaluating the energy consumption and the silicon area of on-chip interconnect architectures
Journal of Systems Architecture: the EUROMICRO Journal
A formal approach to the verification of networks on chip
EURASIP Journal on Embedded Systems
Parallel BMDA with an aggregation of probability models
CEC'09 Proceedings of the Eleventh conference on Congress on Evolutionary Computation
An analytical performance model for the Spidergon NoC with virtual channels
Journal of Systems Architecture: the EUROMICRO Journal
The SKB: a semi-completely-connected bus for on-chip systems
NPC'07 Proceedings of the 2007 IFIP international conference on Network and parallel computing
Network-on-chip architecture design based on mesh-of-tree deterministic routing topology
International Journal of High Performance Systems Architecture
Evolutionary-based conflict-free scheduling of collective communications on spidergon NoCs
Proceedings of the 12th annual conference on Genetic and evolutionary computation
Adaptive and deadlock-free tree-based multicast routing for networks-on-chip
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A methodology for design of unbuffered router microarchitecture for S-mesh NoC
NPC'10 Proceedings of the 2010 IFIP international conference on Network and parallel computing
Virtualizing network-on-chip resources in chip-multiprocessors
Microprocessors & Microsystems
An analytical model for Network-on-Chip with finite input buffer
Frontiers of Computer Science in China
NOCS '11 Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip
Asynchronous switching for low-power networks-on-chip
Microelectronics Journal
A reconfigurable computing platform for real time embedded applications
Microprocessors & Microsystems
Network-on-Chip routing algorithms by breaking cycles
ICA3PP'10 Proceedings of the 10th international conference on Algorithms and Architectures for Parallel Processing - Volume Part I
Hunting deadlocks efficiently in microarchitectural models of communication fabrics
Proceedings of the International Conference on Formal Methods in Computer-Aided Design
Design and evaluation of Mesh-of-Tree based Network-on-Chip using virtual channel router
Microprocessors & Microsystems
SMART: a single-cycle reconfigurable NoC for SoC applications
Proceedings of the Conference on Design, Automation and Test in Europe
Exploring topologies for source-synchronous ring-based network-on-chip
Proceedings of the Conference on Design, Automation and Test in Europe
A fast, source-synchronous ring-based network-on-chip design
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
An Analysis of Reducing Communication Delay in Network-on-Chip Interconnect Architecture
Wireless Personal Communications: An International Journal
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Network processor systems on chips meet the speed and flexibility requirements of next-generation internet routers. The octagon on-chip communication architecture, with its cost, performance, and scalability advantages, supports these network processor SOCs.