SMART: a single-cycle reconfigurable NoC for SoC applications

Authors:
Chia-Hsin Owen Chen;Sunghyun Park;Tushar Krishna;Suvinay Subramanian;Anantha P. Chandrakasan;Li-Shiuan Peh
Affiliations:
Massachusettes Institute of Technology, Cambridge, MA;Massachusettes Institute of Technology, Cambridge, MA;Massachusettes Institute of Technology, Cambridge, MA;Massachusettes Institute of Technology, Cambridge, MA;Massachusettes Institute of Technology, Cambridge, MA;Massachusettes Institute of Technology, Cambridge, MA
Venue:
Proceedings of the Conference on Design, Automation and Test in Europe
Year:
2013

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Abstract

As technology scales, SoCs are increasing in core counts, leading to the need for scalable NoCs to interconnect the multiple cores on the chip. Given aggressive SoC design targets, NoCs have to deliver low latency, high bandwidth, at low power and area overheads. In this paper, we propose Single-cycle Multi-hop Asynchronous Repeated Traversal (SMART) NoC, a NoC that reconfigures and tailors a generic mesh topology for SoC applications at runtime. The heart of our SMART NoC is a novel low-swing clockless repeated link circuit embedded within the router crossbars, that allows packets to potentially bypass all the way from source to destination core within a single clock cycle, without being latched at any intermediate router. Our clockless repeater link has been proven in silicon in 45nm SOI. Results show that at 2GHz, we can traverse 8mm within a single cycle, i.e. 8 hops with 1mm cores. We implement the SMART NoC to layout and show that SMART NoC gives 60% latency savings, and 2.2X power savings compared to a baseline mesh NoC.