TheoSim: combining symbolic simulation and theorem proving for hardware verification

Authors:
G. Al Sammane;J. Schmaltz;D. Toma;P. Ostier;D. Borrione
Affiliations:
TIMA Laboratory, VDS Group, Grenoble Cedex, France;TIMA Laboratory, VDS Group, Grenoble Cedex, France;TIMA Laboratory, VDS Group, Grenoble Cedex, France;TIMA Laboratory, VDS Group, Grenoble Cedex, France;TIMA Laboratory, VDS Group, Grenoble Cedex, France
Venue:
SBCCI '04 Proceedings of the 17th symposium on Integrated circuits and system design
Year:
2004

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Abstract

TheoSim is a symbolic verifiation tool that fills the gap between the simulation of test cases, and the use of theorem provers, for the validation of initial specifications, and the exploration of the very first design steps of digital integrated systems. The principles of Theosim are presented, followed by its application to the verification of the first design step of a state-of-the-art network on chip architecture.