An analytical model for Network-on-Chip with finite input buffer

Authors:
Jian Wang;Yu-Bai Li;Chang Wu
Affiliations:
Didital Signal Processing Lab, School of Communication and Information Engineering, University of Electronic Science and Technology of China, Chengdu, China 610054;Didital Signal Processing Lab, School of Communication and Information Engineering, University of Electronic Science and Technology of China, Chengdu, China 610054;Didital Signal Processing Lab, School of Communication and Information Engineering, University of Electronic Science and Technology of China, Chengdu, China 610054
Venue:
Frontiers of Computer Science in China
Year:
2011

Citing 17
Cited 1

Introduction to queueing networks

Introduction to queueing networks
Performance Analysis of k-ary n-cube Interconnection Networks

IEEE Transactions on Computers
Stochastic models in queueing theory

Stochastic models in queueing theory
A generic architecture for on-chip packet-switched interconnections

DATE '00 Proceedings of the conference on Design, automation and test in Europe
Route packets, not wires: on-chip inteconnection networks

Proceedings of the 38th annual Design Automation Conference
An Interconnect Architecture for Networking Systems on Chips

IEEE Micro
Limits on Interconnection Network Performance

IEEE Transactions on Parallel and Distributed Systems
Performance Analysis of Mesh Interconnection Networks with Deterministic Routing

IEEE Transactions on Parallel and Distributed Systems
A Network on Chip Architecture and Design Methodology

ISVLSI '02 Proceedings of the IEEE Computer Society Annual Symposium on VLSI
On-chip networks: A scalable, communication-centric embedded system design paradigm

VLSID '04 Proceedings of the 17th International Conference on VLSI Design
An Interconnect Channel Design Methodology for High Performance Integrated Circuits

Proceedings of the conference on Design, automation and test in Europe - Volume 2
Structured interconnect architecture: a solution for the non-scalability of bus-based SoCs

Proceedings of the 14th ACM Great Lakes symposium on VLSI
Performance Evaluation and Design Trade-Offs for Network-on-Chip Interconnect Architectures

IEEE Transactions on Computers
Efficient link capacity and QoS design for network-on-chip

Proceedings of the conference on Design, automation and test in Europe: Proceedings
Computation and communication refinement for multiprocessor SoC design: A system-level perspective

Proceedings of the 41st annual Design Automation Conference
Quantum-like effects in network-on-chip buffers behavior

Proceedings of the 44th annual Design Automation Conference
System-Level Buffer Allocation for Application-Specific Networks-on-Chip Router Design

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Analytical performance modeling of shuffle-exchange inspired mesh-based Network-on-Chips

Performance Evaluation

Quantified Score

Hi-index	0.00

Visualization

Abstract

An analytical model is proposed for input buffer router architecture Network-on-Chip (NoC) with finite size buffers. The model is developed based on M/G/1/K queuing theory and takes into consideration the restriction of buffer sizes in NoC. It analyzes the packet's sojourn time in each buffer and calculates the packets average latency in NoC The validity of the model is verified through simulation. By comparing our analytical outcomes to the simulation results, we show that the proposed model successfully captures the performance characteristics of NoC, which provides an efficient performance analysis tool for NoC design.