An Energy-Efficient Reconfigurable Circuit-Switched Network-on-Chip
IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 3 - Volume 04
Key research problems in NoC design: a holistic perspective
CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Constraint-driven bus matrix synthesis for MPSoC
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Improving routing efficiency for network-on-chip through contention-aware input selection
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
COSMECA: application specific co-synthesis of memory and communication architectures for MPSoC
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Bounded arbitration algorithm for QoS-supported on-chip communication
CODES+ISSS '06 Proceedings of the 4th international conference on Hardware/software codesign and system synthesis
The Power of Priority: NoC Based Distributed Cache Coherency
NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
Routing table minimization for irregular mesh NoCs
Proceedings of the conference on Design, automation and test in Europe
Run-time adaptive on-chip communication scheme
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
DNCOCO'07 Proceedings of the 9th WSEAS International Conference on Data Networks, Communications, Computers
QoS-supported on-chip communication for multi-processors
International Journal of Parallel Programming - Special Issue on Multiprocessor-based embedded systems
ADAM: run-time agent-based distributed application mapping for on-chip communication
Proceedings of the 45th annual Design Automation Conference
Real-Time Communication Analysis for On-Chip Networks with Wormhole Switching
NOCS '08 Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip
Minimizing virtual channel buffer for routers in on-chip communication architectures
Proceedings of the conference on Design, automation and test in Europe
ODOR: a microresonator-based high-performance low-cost router for optical networks-on-Chip
CODES+ISSS '08 Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis
A decentralised task mapping approach for homogeneous multiprocessor network-on-chips
International Journal of Reconfigurable Computing - Selected papers from ReCoSoc08
Outstanding research problems in NoC design: system, microarchitecture, and circuit perspectives
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A method for calculating hard QoS guarantees for Networks-on-Chip
Proceedings of the 2009 International Conference on Computer-Aided Design
Communication-aware heuristics for run-time task mapping on NoC-based MPSoC platforms
Journal of Systems Architecture: the EUROMICRO Journal
PMCNOC: A Pipelining Multi-channel Central Caching Network-on-chip Communication Architecture Design
Journal of Signal Processing Systems
Performability/energy tradeoff in error-control schemes for on-chip networks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A hardwired NoC infrastructure for embedded systems on FPGAs
Microprocessors & Microsystems
An analytical model for Network-on-Chip with finite input buffer
Frontiers of Computer Science in China
Performance and complexity analysis of credit-based end-to-end flow control in network-on-chip
ISPA'07 Proceedings of the 5th international conference on Parallel and Distributed Processing and Applications
Mapping on multi/many-core systems: survey of current and emerging trends
Proceedings of the 50th Annual Design Automation Conference
Microprocessors & Microsystems
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As chip complexity grows, design productivity boost is expectedfrom reuse of large parts and blocks of previous designswith the design effort largely invested into the new parts.More and more processor cores and large, reusable componentsare being integrated on a single silicon die but reuseof the communication infrastructure has been difficult. Busesand point to point connections, that have been the main meansto connect components on a chip today, will not result in ascalable platform architecture for the billion transistor chipera. Buses can cost efficiently connect a few tens of components.Point to point connections between communicationpartners is practical for even fewer components. As more andmore components are integrated on a single silicon die, performancebottlenecks of long, global wires preclude reuse ofbuses. Therefore, scalable on-chip communication infrastructureis playing an increasingly dominant role in system-on-chipdesigns. With the super-abundance of cheap, function-specificIP cores, design effort will focus on the weakest link:efficient on-chip communication.Future on-chip communication infrastructure will overcomethe limits of bus-based systems by providing higher bandwidth,higher flexibility and by solving the clock skew problemon large chips. It may, however, present new problems:higher power consumption of the communication infrastructureand harder-to-predict performance patterns. Solutionsto these problems may result in a complete overhaul of SOCdesign methodologies into a communication-centric designstyle. The envisioning of upcoming problems and possiblebenefits has led to intensified research in the field of what iscalled NoCs: Networks on Chips. The term NoCs is used in abroad meaning, encompassing the hardware communicationinfrastructure, the middleware and operating system communicationservices, and a design methodology and tools to mapapplications onto a network on chip. This paper discussestrends in system-on-chip designs, critiques problems and opportunitiesof the NoC paradigm, summarizes research activities,and outlines several directions for future research.