An extendible approach for analyzing fixed priority hard real-time tasks
Real-Time Systems
A Priority-Driven Flow Control Mechanism for Real-Time Traffic in Multiprocessor Networks
IEEE Transactions on Parallel and Distributed Systems
Scheduling Algorithms for Multiprogramming in a Hard-Real-Time Environment
Journal of the ACM (JACM)
Route packets, not wires: on-chip inteconnection networks
Proceedings of the 38th annual Design Automation Conference
Powering networks on chips: energy-efficient and reliable interconnect design for SoCs
Proceedings of the 14th international symposium on Systems synthesis
Interconnection Networks: An Engineering Approach
Interconnection Networks: An Engineering Approach
IEEE Transactions on Parallel and Distributed Systems
Throttle and Preempt: A New Flow Control for Real-Time Communications in Wormhole Networks
ICPP '97 Proceedings of the international Conference on Parallel Processing
A Real-Time Communication Method for Wormhole Switching Networks
ICPP '98 Proceedings of the 1998 International Conference on Parallel Processing
Priority Based Real-Time Communication for Large Scale Wormhole Networks
Proceedings of the 8th International Symposium on Parallel Processing
On-chip networks: A scalable, communication-centric embedded system design paradigm
VLSID '04 Proceedings of the 17th International Conference on VLSI Design
Feasibility analysis of messages for on-chip networks using wormhole routing
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
A survey of research and practices of Network-on-chip
ACM Computing Surveys (CSUR)
A method for calculating hard QoS guarantees for Networks-on-Chip
Proceedings of the 2009 International Conference on Computer-Aided Design
Scheduling framework for real-time dependable NoC-based systems
SOC'09 Proceedings of the 11th international conference on System-on-chip
Static timing analysis for modeling QoS in networks-on-chip
Journal of Parallel and Distributed Computing
Temporal isolation on multiprocessing architectures
Proceedings of the 48th Design Automation Conference
Real-time communication analysis for networks with two-stage arbitration
EMSOFT '11 Proceedings of the ninth ACM international conference on Embedded software
Towards network-on-chip agreement protocols
Proceedings of the tenth ACM international conference on Embedded software
Analytical approaches for performance evaluation of networks-on-chip
Proceedings of the 2012 international conference on Compilers, architectures and synthesis for embedded systems
Mathematical formalisms for performance evaluation of networks-on-chip
ACM Computing Surveys (CSUR)
Designing best effort networks-on-chip to meet hard latency constraints
ACM Transactions on Embedded Computing Systems (TECS) - Special Section on Wireless Health Systems, On-Chip and Off-Chip Network Architectures
Are virtual channels the bottleneck of priority-aware wormhole-switched NoC-based many-cores?
Proceedings of the 21st International conference on Real-Time Networks and Systems
NoC contention analysis using a branch-and-prune algorithm
ACM Transactions on Embedded Computing Systems (TECS) - Special Issue on Design Challenges for Many-Core Processors, Special Section on ESTIMedia'13 and Regular Papers
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In this paper, we discuss a real-time on-chip communication service with a priority-based wormhole switching policy. A novel off-line schedulability analysis approach is presented. By evaluating diverse inter-relationships among the traffic-flows, this approach can predict the packet network latency based on two quantifiable different delays: direct interference from higher priority traffic-flows and indirect interference from other higher priority traffic-flows. Due to the inevitable existence of parallel interference, we prove that the general problem of determining the exact schedulability of real-time traffic-flow over the onchip network is NP-hard. However the results presented do form an upper bound. In addition, an error in a previous published scheduling approach is illustrated and remedied. Utilizing this analysis scheme, we can flexibly evaluate at design time the schedulability of a set of traffic-flows with different QoS requirements on a real-time SoC/NoC communication platform.