An extendible approach for analyzing fixed priority hard real-time tasks
Real-Time Systems
Holistic schedulability analysis for distributed hard real-time systems
Microprocessing and Microprogramming - Parallel processing in embedded real-time systems
A comprehensive analytical model for wormhole routing in multicomputer systems
Journal of Parallel and Distributed Computing
The iSLIP scheduling algorithm for input-queued switches
IEEE/ACM Transactions on Networking (TON)
Symmetric Crossbar Arbiters for VLSI Communication Switches
IEEE Transactions on Parallel and Distributed Systems
Journal of Parallel and Distributed Computing
Proceedings of the conference on Design, automation and test in Europe - Volume 2
QNoC: QoS architecture and design process for network on chip
Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Networks on chip
Principles and Practices of Interconnection Networks
Principles and Practices of Interconnection Networks
A unified approach to constrained mapping and routing on network-on-chip architectures
CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Æthereal Network on Chip: Concepts, Architectures, and Implementations
IEEE Design & Test
Switch Scheduling and Network Design for Real-Time Systems
RTAS '06 Proceedings of the 12th IEEE Real-Time and Embedded Technology and Applications Symposium
Analytical router modeling for networks-on-chip performance analysis
Proceedings of the conference on Design, automation and test in Europe
Improved response time analysis of tasks scheduled under preemptive Round-Robin
CODES+ISSS '07 Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Globally-Synchronized Frames for Guaranteed Quality-of-Service in On-Chip Networks
ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture
Real-Time Communication Analysis for On-Chip Networks with Wormhole Switching
NOCS '08 Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip
A Switch Design for Real-Time Industrial Networks
RTAS '08 Proceedings of the 2008 IEEE Real-Time and Embedded Technology and Applications Symposium
Providing accurate event models for the analysis of heterogeneous multiprocessor systems
CODES+ISSS '08 Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis
A recursive approach to end-to-end path latency computation in heterogeneous multiprocessor systems
CODES+ISSS '09 Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Outstanding research problems in NoC design: system, microarchitecture, and circuit perspectives
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A method for calculating hard QoS guarantees for Networks-on-Chip
Proceedings of the 2009 International Conference on Computer-Aided Design
Network calculus: a theory of deterministic queuing systems for the internet
Network calculus: a theory of deterministic queuing systems for the internet
Back Suction: Service Guarantees for Latency-Sensitive On-chip Networks
NOCS '10 Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip
Proceedings of the Conference on Design, Automation and Test in Europe
NoC Switch with Credit Based Guaranteed Service Support Qualified for GALS Systems
DSD '10 Proceedings of the 2010 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools
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Current on-chip and macro networks use multi-stage arbitration schemes which independently assign different resources such as crossbar inputs and outputs to individual traffic streams. To use these networks in real-time systems, their worst-case behavior must be proved analytically in order to ensure the required timing guarantees. Current analysis approaches, however, do not capture the multi-stage arbitration accurately. In this paper, we propose an analysis that maps the multi-stage arbitration to a schedulability analysis of multiprocessors with shared resources. This allows the exploitation of knowledge about the worst-case behavior of the individual traffic streams, which is required to provide nonsymmetric guarantees. Using this scheduling analysis approach, a detailed analysis solution for a common multi-stage arbitration scheme (iSLIP) is presented. Finally, we evaluate the proposed approach experimentally and compare it to previous work.