Communications of the ACM - Special section on computer architecture
Concert: design of a multiprocessor development system
ISCA '86 Proceedings of the 13th annual international symposium on Computer architecture
Computer
Analysis of interconnection networks with different arbiter designs
Journal of Parallel and Distributed Computing
Multicomputer networks: message-based parallel processing
Multicomputer networks: message-based parallel processing
ISCA '88 Proceedings of the 15th Annual International Symposium on Computer architecture
High-performance multi-queue buffers for VLSI communications switches
ISCA '88 Proceedings of the 15th Annual International Symposium on Computer architecture
Finite-grain message passing concurrent computers
C3P Proceedings of the third conference on Hypercube concurrent computers and applications: Architecture, software, computer systems, and general issues - Volume 1
Performance Analysis of Multibuffered Packet-Switching Networks in Multiprocessor Systems
IEEE Transactions on Computers
ISCA '90 Proceedings of the 17th annual international symposium on Computer Architecture
ISCA '85 Proceedings of the 12th annual international symposium on Computer architecture
Simulation Techniques for Discrete Event Systems
Simulation Techniques for Discrete Event Systems
Probabilistic analysis of a crossbar switch
ISCA '82 Proceedings of the 9th annual symposium on Computer Architecture
Pipelined memory shared buffer for VLSI switches
SIGCOMM '95 Proceedings of the conference on Applications, technologies, architectures, and protocols for computer communication
A Cost and Speed Model for k-ary n-Cube Wormhole Routers
IEEE Transactions on Parallel and Distributed Systems
IEEE/ACM Transactions on Networking (TON)
Architecture Scalability of Parallel Vector Computers with a Shared Memory
IEEE Transactions on Computers
Low-level router design and its impact on supercomputer system performance
ICS '99 Proceedings of the 13th international conference on Supercomputing
The iSLIP scheduling algorithm for input-queued switches
IEEE/ACM Transactions on Networking (TON)
A VLSI wrapped wave front arbiter for crossbar switches
GLSVLSI '01 Proceedings of the 11th Great Lakes symposium on VLSI
HIPIQS: A High-Performance Switch Architecture Using Input Queuing
IEEE Transactions on Parallel and Distributed Systems
A comparative study of arbitration algorithms for the Alpha 21364 pipelined router
Proceedings of the 10th international conference on Architectural support for programming languages and operating systems
Developing Micropipeline Wavefront Arbiters
IEEE Design & Test
Spider: A High-Speed Network Interconnect
IEEE Micro
Routers with a single stage of buffering
Proceedings of the 2002 conference on Applications, technologies, architectures, and protocols for computer communications
The Least Choice First Scheduling Method for High-Speed Network Switche
IPDPS '02 Proceedings of the 16th International Parallel and Distributed Processing Symposium
Investigating Switch Scheduling Algorithms to Support QoS in the Multimedia Router
IPDPS '02 Proceedings of the 16th International Parallel and Distributed Processing Symposium
Shortest and Oldest First Non-interleaving Packet Switching Scheduling Algorithm
ICOIN '02 Revised Papers from the International Conference on Information Networking, Wireless Communications Technologies and Network Applications-Part I
A hierarchical modeling framework for on-chip communication architectures
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Bounds on delays and queue lengths in input-queued cell switches
Journal of the ACM (JACM)
On the performance of input-queued cell-based switches with two priority classes
ICCC '02 Proceedings of the 15th international conference on Computer communication
The limits of input-queued switch performance with future packet arrival information
Computer Networks: The International Journal of Computer and Telecommunications Networking
Scaling internet routers using optics
Proceedings of the 2003 conference on Applications, technologies, architectures, and protocols for computer communications
ATM cell scheduling with queue length-based priority scheme
ICCCN '95 Proceedings of the 4th International Conference on Computer Communications and Networks
Impact of Switch Design on the Application Performance of Cache-Coherent Multiprocessors
IPPS '98 Proceedings of the 12th. International Parallel Processing Symposium on International Parallel Processing Symposium
On achieving throughput in an input-queued switch
IEEE/ACM Transactions on Networking (TON)
Traffic Scheduling Solutions with QoS Support for an Input-Buffered MultiMedia Router
IEEE Transactions on Parallel and Distributed Systems
On guaranteed smooth scheduling for input-queued switches
IEEE/ACM Transactions on Networking (TON)
MMR: A MultiMedia Router architecture to support hybrid workloads
Journal of Parallel and Distributed Computing
High-performance switching based on buffered crossbar fabrics
Computer Networks: The International Journal of Computer and Telecommunications Networking
Node-disjoint paths in hierarchical hypercube networks
Information Sciences: an International Journal
Computer Networks: The International Journal of Computer and Telecommunications Networking
Low-latency scheduling in large switches
Proceedings of the 3rd ACM/IEEE Symposium on Architecture for networking and communications systems
A logarithmic scheduling algorithm for high speed input-queued switches
Computer Communications
Rate and delay guarantees provided by Clos packet switches with load balancing
IEEE/ACM Transactions on Networking (TON)
Matching from the first iteration: an iterative switching algorithm for an input queued switch
IEEE/ACM Transactions on Networking (TON)
High-radix crossbar switches enabled by proximity communication
Proceedings of the 2008 ACM/IEEE conference on Supercomputing
Allocator implementations for network-on-chip routers
Proceedings of the Conference on High Performance Computing Networking, Storage and Analysis
The least choice first (LCF) scheduling method for high-speed network switches
The least choice first (LCF) scheduling method for high-speed network switches
Design of the switching controller for the high-capacity non-blocking internet router
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Backlog aware scheduling for ingress memories in high-radix, single-stage switches
GLOBECOM'09 Proceedings of the 28th IEEE conference on Global telecommunications
Scalable alternatives to virtual output queuing
ICC'09 Proceedings of the 2009 IEEE international conference on Communications
Distributed WFQ scheduling converging to weighted max-min fairness
Computer Networks: The International Journal of Computer and Telecommunications Networking
VLSI micro-architectures for high-radix crossbar schedulers
NOCS '11 Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip
Real-time communication analysis for networks with two-stage arbitration
EMSOFT '11 Proceedings of the ninth ACM international conference on Embedded software
An 8 × 8 20 Gbps Reconfigurable Load Balanced TDM Switch IC for High-Speed Networking
Journal of Signal Processing Systems
A new hardware efficient link scheduling algorithm to guarantee qos on clusters
Euro-Par'05 Proceedings of the 11th international Euro-Par conference on Parallel Processing
Packet chaining: efficient single-cycle allocation for on-chip networks
Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture
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The design and implementation of symmetric crossbar arbiters are addressed. Severalarbiter designs are compared based on simulations of a multistage interconnectionnetwork. These simulations demonstrate the influence of the switch arbitration policy onnetwork throughput, average latency, and worst-case latency. It is shown that somenatural designs result in poor system performance and/or slow implementations. Twoefficient arbiter implementations are proposed. Based on network simulations, VLSIimplementation, and circuit simulation, it is shown that these arbiters achieve nearlyoptimal system performance without becoming the critical path that limits the systemclock.