High-speed switch scheduling for local-area networks
ACM Transactions on Computer Systems (TOCS)
Scheduling algorithms for input-queued cell switches
Scheduling algorithms for input-queued cell switches
The iSLIP scheduling algorithm for input-queued switches
IEEE/ACM Transactions on Networking (TON)
Symmetric Crossbar Arbiters for VLSI Communication Switches
IEEE Transactions on Parallel and Distributed Systems
Scheduling nonuniform traffic in high speed packet switches and routers
Scheduling nonuniform traffic in high speed packet switches and routers
Issues and trends in router design
IEEE Communications Magazine
Matching output queueing with a combined input/output-queued switch
IEEE Journal on Selected Areas in Communications
Output-queued switch emulation by fabrics with limited memory
IEEE Journal on Selected Areas in Communications
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As buffer-less crossbar scheduling algorithms reach their practical limitations due to higher port numbers and data rates, internally buffered crossbar (IBC) switches have gained a lot of interest recently due to their great potential in solving the complexity and scalability issues faced by their buffer-less predecessors. The IBC switching architecture combined with the virtual output queueing (VOQ) architecture was shown, through distributed scheduling algorithms, to be able to sustain the current and expected increases in Internet throughput rates. Due to the architectural similarity between the input queued (IQ) and IBC switches, all the algorithms proposed for the latter were just a simple mapping of earlier algorithms proposed for the former. In this paper, we propose a set of scheduling schemes that are purely advocated for the VOQ/IBC switch architecture. We first address the issue of the internal buffers importance in the arbitration process. We propose a weighted scheduling algorithm, named Critical internal Buffer First (CBF), which takes full advantage of the internal buffer elements and makes its decision exclusively on the internal buffer information. Second, in order to simplify the scheduling scheme and make it practical, we propose a class of scheduling algorithms, named Current Arrival First-Priority Removal (CAF-PRMV) that use priority levels instead of weights. We argue that the interaction, through the internal buffer element, between the input and output schedulers is very important in designing such practical and highly scalable schemes for the IBC switching architecture. Our hardware implementation, in reconfigurable logic, shows that our CAF-PRMV class of algorithms can sustain a 10 Gbps line speed for a 32 × 32 VOQ/IBC switch.