Communications of the ACM - Special section on computer architecture
Multicomputer networks: message-based parallel processing
Multicomputer networks: message-based parallel processing
ISCA '85 Proceedings of the 12th annual international symposium on Computer architecture
VLSI Communication Components for Multicomputer Networks
VLSI Communication Components for Multicomputer Networks
Using feedback to control tree saturation in multistage interconnection networks
ISCA '89 Proceedings of the 16th annual international symposium on Computer architecture
Dynamically-Allocated Multi-Queue Buffers for VLSI Communication Switches
IEEE Transactions on Computers
High speed switch scheduling for local area networks
ASPLOS V Proceedings of the fifth international conference on Architectural support for programming languages and operating systems
High-speed switch scheduling for local-area networks
ACM Transactions on Computer Systems (TOCS)
Segment router: a novel router design for parallel computers
SPAA '94 Proceedings of the sixth annual ACM symposium on Parallel algorithms and architectures
IEEE Transactions on Computers
Using a Multipath Network for Reducing the Effects of Hot Spots
IEEE Transactions on Parallel and Distributed Systems
Prevention of Congestion in Packet-Switched Multistage Interconnection Networks
IEEE Transactions on Parallel and Distributed Systems
Pipelined memory shared buffer for VLSI switches
SIGCOMM '95 Proceedings of the conference on Applications, technologies, architectures, and protocols for computer communication
Design and Analysis of High Performance Multistage Interconnection Networks
IEEE Transactions on Computers
Proceedings of the 24th annual international symposium on Computer architecture
Stability results for networks with input and output blocking
STOC '98 Proceedings of the thirtieth annual ACM symposium on Theory of computing
The iSLIP scheduling algorithm for input-queued switches
IEEE/ACM Transactions on Networking (TON)
ISCA '90 Proceedings of the 17th annual international symposium on Computer Architecture
IEEE Transactions on Parallel and Distributed Systems
Packet-mode scheduling in input-queued cell-based switches
IEEE/ACM Transactions on Networking (TON)
Inside Parallel Computers: Trends in Interconnection Networks
IEEE Computational Science & Engineering
Tiny Tera: A Packet Switch Core
IEEE Micro
The Use of Feedback in Multiprocessors and Its Application to Tree Saturation Control
IEEE Transactions on Parallel and Distributed Systems
IEEE Transactions on Parallel and Distributed Systems
Symmetric Crossbar Arbiters for VLSI Communication Switches
IEEE Transactions on Parallel and Distributed Systems
The Least Choice First Scheduling Method for High-Speed Network Switche
IPDPS '02 Proceedings of the 16th International Parallel and Distributed Processing Symposium
Integrated Provision of QoS Guarantees to Unicast and Multicast Traffic in Packet Switches
IWDC '01 Proceedings of the Thyrrhenian International Workshop on Digital Communications: Evolutionary Trends of the Internet
Pipelined Multi-Queue Management in a VLSI ATM Switch Chip with Credit-Based Flow-Control
ARVLSI '97 Proceedings of the 17th Conference on Advanced Research in VLSI (ARVLSI '97)
Analysis of Buffer Design for Adaptive Routing in Direct Networks
MASCOTS '96 Proceedings of the 4th International Workshop on Modeling, Analysis, and Simulation of Computer and Telecommunications Systems
A modular simulation framework for architectural exploration of on-chip interconnection networks
Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Design and Implementation of High-Performance Memory Systems for Future Packet Buffers
Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
IBM Journal of Research and Development
FIFO-Based Multicast Scheduling Algorithm for Virtual Output Queued Packet Switches
IEEE Transactions on Computers
A DRAM/SRAM Memory Scheme for Fast Packet Buffers
IEEE Transactions on Computers
A survey of research and practices of Network-on-chip
ACM Computing Surveys (CSUR)
Towards an efficient switch architecture for high-radix switches
Proceedings of the 2006 ACM/IEEE symposium on Architecture for networking and communications systems
ViChaR: A Dynamic Virtual Channel Regulator for Network-on-Chip Routers
Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture
Modeling, Simulation and Performance Evaluation for a CIOQ Switch Architecture
ANSS '06 Proceedings of the 39th annual Symposium on Simulation
Computer Networks: The International Journal of Computer and Telecommunications Networking
Proceedings of the 3rd ACM/IEEE Symposium on Architecture for networking and communications systems
Design issues in next-generation merchant switch fabrics
IEEE/ACM Transactions on Networking (TON)
ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture
A dynamically-allocated virtual channel architecture with congestion awareness for on-chip routers
Proceedings of the 45th annual Design Automation Conference
Trends in highly scalable crossbar-based packet switch architecture
Computer Communications
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Router with centralized buffer for network-on-chip
Proceedings of the 19th ACM Great Lakes symposium on VLSI
Performance analysis of small non-uniform packet switches
Performance Evaluation
Bandwidth guaranteed multicast scheduling for virtual output queued packet switches
Journal of Parallel and Distributed Computing
Performance evaluation of new scheduling methods for the RR/RR CICQ switch
Computer Communications
SCARAB: a single cycle adaptive routing and bufferless network
Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture
Light speed arbitration and flow control for nanophotonic interconnects
Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture
The least choice first (LCF) scheduling method for high-speed network switches
The least choice first (LCF) scheduling method for high-speed network switches
Design and implementation of switch module for NS-3
Proceedings of the Fourth International ICST Conference on Performance Evaluation Methodologies and Tools
Accelerated packet placement architecture for parallel shared memory routers
NETWORKING'07 Proceedings of the 6th international IFIP-TC6 conference on Ad Hoc and sensor networks, wireless networks, next generation internet
Crosstalk-preventing scheduling in AWG-based cell switches
GLOBECOM'09 Proceedings of the 28th IEEE conference on Global telecommunications
Trace-driven optimization of networks-on-chip configurations
Proceedings of the 47th Design Automation Conference
Microprocessors & Microsystems
A monitor interconnect and support subsystem for multicore processors
Proceedings of the Conference on Design, Automation and Test in Europe
Achieving 100% throughput in an input-queued switch
INFOCOM'96 Proceedings of the Fifteenth annual joint conference of the IEEE computer and communications societies conference on The conference on computer communications - Volume 1
Feedback-based scheduling for load-balanced two-stage switches
IEEE/ACM Transactions on Networking (TON)
HiPC'05 Proceedings of the 12th international conference on High Performance Computing
Delay performance analysis for an agile all-photonic star network
NETWORKING'06 Proceedings of the 5th international IFIP-TC6 conference on Networking Technologies, Services, and Protocols; Performance of Computer and Communication Networks; Mobile and Wireless Communications Systems
Efficient trace-driven metaheuristics for optimization of networks-on-chip configurations
Proceedings of the International Conference on Computer-Aided Design
Saturating the transceiver bandwidth: switch fabric design on FPGAs
Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays
New round-robin scheduling algorithm for combined input-crosspoint buffered switch
ICN'05 Proceedings of the 4th international conference on Networking - Volume Part I
Scheduling algorithms for input queued switches using local search technique
ICN'05 Proceedings of the 4th international conference on Networking - Volume Part I
Flexible router architecture for network-on-chip
Computers & Mathematics with Applications
APCR: an adaptive physical channel regulator for on-chip interconnects
Proceedings of the 21st international conference on Parallel architectures and compilation techniques
An efficient single-iteration single-bit request scheduling algorithm for input-queued switches
Journal of Network and Computer Applications
MSMPS packet scheduling algorithm for VOQ switches
Proceedings of the 24th International Teletraffic Congress
Integrating microsecond circuit switching into the data center
Proceedings of the ACM SIGCOMM 2013 conference on SIGCOMM
Graceful deadlock-free fault-tolerant routing algorithm for 3D Network-on-Chip architectures
Journal of Parallel and Distributed Computing
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Small nxn switches are key components of multistage interconnection networks used in multiprocessors as well as in the communication coprocessors used in multicomputers. The design of the internal buffers in these switches is of critical importance for achieving high throughput low latency communication. We discuss several buffer structures and compare them in terms of implementation complexity and their ability to deal with variations in traffic patterns and message lengths. We present a new design of buffers that provide non-FIFO message handling and efficient storage allocation for variable size packets through the use of linked lists managed by a simple on-chip controller. We evaluate the new buffer design by comparing it to several alternative designs in the context of a multi-stage interconnection network. Our modeling and simulations show that the new buffer outperforms its “competition” and can thus be used to improve the performance of a wide variety of systems currently using less efficient buffers.