High-performance multi-queue buffers for VLSI communications switches
ISCA '88 Proceedings of the 15th Annual International Symposium on Computer architecture
High-speed switch scheduling for local-area networks
ACM Transactions on Computer Systems (TOCS)
Scheduling algorithms for input-queued cell switches
Scheduling algorithms for input-queued cell switches
The iSLIP scheduling algorithm for input-queued switches
IEEE/ACM Transactions on Networking (TON)
Current issues in packet switch design
ACM SIGCOMM Computer Communication Review
Scaling internet routers using optics
Proceedings of the 2003 conference on Applications, technologies, architectures, and protocols for computer communications
The load-balanced router
Padded frames: a novel algorithm for stable scheduling in load-balanced switches
IEEE/ACM Transactions on Networking (TON)
Minimizing internal speedup for performance guaranteed switches with optical fabrics
IEEE/ACM Transactions on Networking (TON)
Simulation of a ultra-wide band enhanced time difference of arrival system
PDCS '07 Proceedings of the 19th IASTED International Conference on Parallel and Distributed Computing and Systems
Achieving 100% throughput in an input-queued switch
INFOCOM'96 Proceedings of the Fifteenth annual joint conference of the IEEE computer and communications societies conference on The conference on computer communications - Volume 1
Load balanced Birkhoff-von Neumann switches, part II: multi-stage buffering
Computer Communications
Load balanced Birkhoff-von Neumann switches, part I: one-stage buffering
Computer Communications
Load-balanced three-stage switch
Journal of Network and Computer Applications
An efficient single-iteration single-bit request scheduling algorithm for input-queued switches
Journal of Network and Computer Applications
Data Center Switch for Load Balanced Fat-Trees
Journal of Signal Processing Systems
A Study on the Performance of a Three-Stage Load-Balancing Switch
IEEE/ACM Transactions on Networking (TON)
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A framework for designing feedback-based scheduling algorithms is proposed for elegantly solving the notorious packet missequencing problem of a load-balanced switch. Unlike existing approaches, we show that the efforts made in load balancing and keeping packets in order can complement each other. Specifically, at each middle-stage port between the two switch fabrics of a load-balanced switch, only a single-packet buffer for each virtual output queueing (VOQ) is required. Although packets belonging to the same flow pass through different middle-stage VOQs, the delays they experience at different middle-stage ports will be identical. This is made possible by properly selecting and coordinating the two sequences of switch configurations to form a joint sequence with both staggered symmetry property and in-order packet delivery property. Based on the staggered symmetry property, an efficient feedback mechanism is designed to allow the right middle-stage port occupancy vector to be delivered to the right input port at the right time. As a result, the performance of load balancing as well as the switch throughput is significantly improved. We further extend this feedback mechanism to support the multicabinet implementation of a load-balanced switch, where the propagation delay between switch linecards and switch fabrics is nonnegligible. As compared to the existing load-balanced switch architectures and scheduling algorithms, our solutions impose a modest requirement on switch hardware, but consistently yield better delay-throughput performance. Last but not least, some extensions and refinements are made to address the scalability, implementation, and fairness issues of our solutions.