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Symmetric Crossbar Arbiters for VLSI Communication Switches
IEEE Transactions on Parallel and Distributed Systems
Universal schemes for parallel communication
STOC '81 Proceedings of the thirteenth annual ACM symposium on Theory of computing
Load balanced Birkhoff-von Neumann switches, part II: multi-stage buffering
Computer Communications
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Work-conserving distributed schedulers for Terabit routers
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A DRAM/SRAM Memory Scheme for Fast Packet Buffers
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JumboGen: dynamic jumbo frame generation for network performance scalability
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Frame-aggregated concurrent matching switch
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IEEE/ACM Transactions on Networking (TON)
STOC '08 Proceedings of the fortieth annual ACM symposium on Theory of computing
Proceedings of the ACM workshop on Programmable routers for extensible services of tomorrow
Padded frames: a novel algorithm for stable scheduling in load-balanced switches
IEEE/ACM Transactions on Networking (TON)
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Scalable Model for Packet Loss Analysis of Load-Balancing Switches with Identical Input Processes
ASMTA '09 Proceedings of the 16th International Conference on Analytical and Stochastic Modeling Techniques and Applications
Packet Loss Analysis of Load-Balancing Switch with ON/OFF Input Processes
EPEW '09 Proceedings of the 6th European Performance Engineering Workshop on Computer Performance Engineering
RouteBricks: exploiting parallelism to scale software routers
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PDCS '07 Proceedings of the 19th IASTED International Conference on Parallel and Distributed Computing and Systems
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CR switch: a load-balanced switch with contention and reservation
IEEE/ACM Transactions on Networking (TON)
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ICOIN'09 Proceedings of the 23rd international conference on Information Networking
IEEE/ACM Transactions on Networking (TON)
Towards green broadband access networks
GLOBECOM'09 Proceedings of the 28th IEEE conference on Global telecommunications
Traffic grooming: a changing role in green optical networks
GLOBECOM'09 Proceedings of the 28th IEEE conference on Global telecommunications
Enabling a bufferless core network using edge-to-edge packet-level FEC
INFOCOM'10 Proceedings of the 29th conference on Information communications
Twister networks and their applications to load-balanced switches
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Helios: a hybrid electrical/optical switch architecture for modular data centers
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Motivating future interconnects: a differential measurement analysis of PCI latency
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Packet loss minimization in load-balancing switch
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An Energy Efficient IP over WDM Network
GREENCOM-CPSCOM '10 Proceedings of the 2010 IEEE/ACM Int'l Conference on Green Computing and Communications & Int'l Conference on Cyber, Physical and Social Computing
Feedback-based scheduling for load-balanced two-stage switches
IEEE/ACM Transactions on Networking (TON)
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IEEE/ACM Transactions on Networking (TON)
Optical packet buffers for backbone internet routers
IEEE/ACM Transactions on Networking (TON)
Dynamic topologies for sustainable and energy efficient traffic routing
Computer Networks: The International Journal of Computer and Telecommunications Networking
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IWQoS'05 Proceedings of the 13th international conference on Quality of Service
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LBSR: a load-balanced semiminimal routing algorithm in cellular routers
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IEEE/ACM Transactions on Networking (TON)
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Routers built around a single-stage crossbar and a centralized scheduler do not scale, and (in practice) do not provide the throughput guarantees that network operators need to make efficient use of their expensive long-haul links. In this paper we consider how optics can be used to scale capacity and reduce power in a router. We start with the promising load-balanced switch architecture proposed by C-S. Chang. This approach eliminates the scheduler, is scalable, and guarantees 100% throughput for a broad class of traffic. But several problems need to be solved to make this architecture practical: (1) Packets can be mis-sequenced, (2) Pathological periodic traffic patterns can make throughput arbitrarily small, (3) The architecture requires a rapidly configuring switch fabric, and (4) It does not work when linecards are missing or have failed. In this paper we solve each problem in turn, and describe new architectures that include our solutions. We motivate our work by designing a 100Tb/s packet-switched router arranged as 640 linecards, each operating at 160Gb/s. We describe two different implementations based on technology available within the next three years.