Scheduling algorithms for input-queued cell switches
Scheduling algorithms for input-queued cell switches
On the stability of input-queued switches with speed-up
IEEE/ACM Transactions on Networking (TON)
Analysis of the parallel packet switch architecture
IEEE/ACM Transactions on Networking (TON)
Bounds on delays and queue lengths in input-queued cell switches
Journal of the ACM (JACM)
Scaling internet routers using optics
Proceedings of the 2003 conference on Applications, technologies, architectures, and protocols for computer communications
The load-balanced router
Another Simple Algorithm for Edge-Coloring Bipartite Graphs
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
A Scalable Switch for Service Guarantees
HOTI '05 Proceedings of the 13th Symposium on High Performance Interconnects
Providing guaranteed rate services in the load balanced Birkhoff-von Neumann switches
IEEE/ACM Transactions on Networking (TON)
Logarithmic delay for N × N packet switches under the crossbar constraint
IEEE/ACM Transactions on Networking (TON)
Padded frames: a novel algorithm for stable scheduling in load-balanced switches
IEEE/ACM Transactions on Networking (TON)
Achieving 100% throughput in an input-queued switch
INFOCOM'96 Proceedings of the Fifteenth annual joint conference of the IEEE computer and communications societies conference on The conference on computer communications - Volume 1
Load balanced Birkhoff-von Neumann switches, part II: multi-stage buffering
Computer Communications
Load balanced Birkhoff-von Neumann switches, part I: one-stage buffering
Computer Communications
Matching output queueing with a combined input/output-queued switch
IEEE Journal on Selected Areas in Communications
Randomized scheduling algorithms for high-aggregate bandwidth switches
IEEE Journal on Selected Areas in Communications
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Network operators need high-capacity router architectures that can offer scalability, provide throughput guarantees, and maintain packet ordering. However, current centralized crossbar-based architectures cannot scale to fast line rates and high port counts. On the other hand, while load-balanced switch architectures that rely on two identical stages of fixed configuration meshes appear to be an effective way to scale Internet routers to very high capacities, they incur a large worst-case packet reordering that is at best quadratic to the switch size. In this paper, we introduce the concurrent matching switch (CMS) architecture, which also uses two identical stages of fixed configuration meshes with the same scalability properties as current load-balanced routers. However, by adopting a novel contention-resolution architecture that is scalable and distributed, the CMS architecture enforces packet ordering throughout the switch. Using the CMS architecture, we show that scalability, 100% throughput, packet ordering, and O(1) amortized time complexity with sequential hardware per linecard can all be achieved. We further demonstrate a delay analysis for the CMS architecture.