Load-balanced three-stage switch

  • Authors:
  • Bing Hu;Kwan L. Yeung;Zhaoyang Zhang

  • Affiliations:
  • Department of Information Science and Electronic Engineering, Zhejiang University, Hangzhou, PR China;Department of Electrical and Electronic Engineering, The University of Hong Kong, Hong Kong, PR China;Department of Information Science and Electronic Engineering, Zhejiang University, Hangzhou, PR China

  • Venue:
  • Journal of Network and Computer Applications
  • Year:
  • 2012

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Abstract

A load-balanced two-stage switch is scalable and can provide close to 100% throughput. Its major problem is that packets can be mis-sequenced when they arrive at outputs. In a recent work, the packet mis-sequencing problem is elegantly solved by a feedback-based switch architecture. In this paper, we extend the feedback-based switch from two-stage to three-stage for further cutting down average packet delay while still ensuring in-order packet delivery and close to 100% throughput. The basic idea is to use the third stage switch to map heavy flows to experience less middle-stage delays. To identity heavy flows, an adaptive traffic estimation algorithm is proposed. To ensure max-min fairness in bandwidth allocation under any inadmissible traffic pattern, an efficient fair scheduler is devised.