High-speed switch scheduling for local-area networks
ACM Transactions on Computer Systems (TOCS)
Scheduling algorithms for input-queued cell switches
Scheduling algorithms for input-queued cell switches
Symmetric Crossbar Arbiters for VLSI Communication Switches
IEEE Transactions on Parallel and Distributed Systems
Scaling internet routers using optics
Proceedings of the 2003 conference on Applications, technologies, architectures, and protocols for computer communications
A 20 Gbps Scalable Load-Balanced TDM Switch with CODEC for High Speed Networking Applications
IWSOC '05 Proceedings of the Fifth International Workshop on System-on-Chip for Real-Time Applications
Design of Analog CMOS Integrated Circuits
Design of Analog CMOS Integrated Circuits
A DC-balanced, partitioned-block, 8B/10B transmission code
IBM Journal of Research and Development
A synchronous 50% duty-cycle clock generator in 0.35-µm CMOS
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Load balanced Birkhoff-von Neumann switches, part I: one-stage buffering
Computer Communications
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In this paper, we propose a reconfigurable load balanced symmetric TDM switch fabric. We fold this two-stage switch to reduce 50% hardware complexity, and then implement a 3.65 mm驴脳驴3.57 mm prototype switch fabric IC, including a digital 8驴脳驴8 switch core, eight 16B20B CODECs, eight SERDES ports, eight CML I/O interfaces and a PLL, in 0.18 μm CMOS technology. The digital 8驴脳驴8 switch core has reconfigurable connection patterns for the ease of scaling up to an N脳N switch (N is power of 4). We propose the 16B20B CODEC scheme to reduce the switch core clock rate by half. In the SERDES, we employ the half-rate scheme and then use static CMOS gates for the low power consumption. We develop a low power, area-efficient and wide-band CML I/O interface with our patented PMOS active load inductive-peaking scheme for high-speed data transmission. With the 16B20B CODEC, the half-rate, and the PMOS active load schemes, almost 50% of the power is saved as compared with the design of the 8B10B CODEC, the full-rate and on-chip inductors CML schemes. Our measurement shows that an 8驴脳驴8 switch fabric IC can achieve 20 Gbps switching rate and consumes only about 690 mW power. A terabit switch fabric can then be constructed by cascading the designed switch ICs.