High-speed switch scheduling for local-area networks
ACM Transactions on Computer Systems (TOCS)
On the self-similar nature of Ethernet traffic (extended version)
IEEE/ACM Transactions on Networking (TON)
Broadband integrated networks
The iSLIP scheduling algorithm for input-queued switches
IEEE/ACM Transactions on Networking (TON)
On the stability of input-queued switches with speed-up
IEEE/ACM Transactions on Networking (TON)
Performance Guarantees in Communication Networks
Performance Guarantees in Communication Networks
Scaling internet routers using optics
Proceedings of the 2003 conference on Applications, technologies, architectures, and protocols for computer communications
On the speedup required for combined input- and output-queued switching
Automatica (Journal of IFAC)
Load balanced Birkhoff-von Neumann switches, part II: multi-stage buffering
Computer Communications
Load balanced Birkhoff-von Neumann switches, part I: one-stage buffering
Computer Communications
An approximation method of origin-destination flow traffic from link load counts
Computers and Electrical Engineering
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The load-balanced (LB) switch proposed by C.S. Chang et al. [1], [2] consists of two stages. First, a load-balancing stage converts arriving packets into uniform traffic. Then, a forwarding stage transfers packets from the linecards to their final output destination. Load-balanced switches do not need a centralized scheduler and can achieve 100% throughput for a broad class of traffic distributions. However, load-balanced switches may cause packets at the output port to be out of sequence. Several schemes have been proposed to tackle the out-of-sequence problem of the load-balanced switch. They are either too complex to implement, or introduce a large additional delay. In this paper, we present a practical load-balanced switch, called the Byte-Focal switch, which uses packet-by-packet scheduling to significantly improve the delay performance over switches of comparable complexity. We prove that the queues at the input need only finite buffering, and that the overall switch is stable under any traffic matrix. Our analysis shows that the average queuing delay is roughly linear with the switch size N, and although the worst case resequencing delay is N2, the average resequencing delay is much smaller. This means that we can reduce the required resequencing buffer size significantly.