On the speedup required for combined input- and output-queued switching

  • Authors:

  • Balaji Prabhakar;Nick McKeown

  • Affiliations:

  • Departments of Electrical Engineering and Computer Science, Stanford University, Stanford, CA 94305, USA;Departments of Electrical Engineering and Computer Science, Stanford University, Stanford, CA 94305, USA

  • Venue:
  • Automatica (Journal of IFAC)
  • Year:
  • 1999

Quantified Score

Hi-index 22.15

Visualization

Abstract

Architectures based on a non-blocking fabric, such as a crosspoint switch, are attractive for use in high-speed LAN switches, IP routers, and ATM switches. When operating at the highest speed, memory bandwidth limitations dictate that queues be placed at the input of the switch. But it is well known that input-queueing can lead to low throughput, and does not allow the control of latency through the switch. This is in contrast to output-queueing which maximizes throughput and permits the accurate control of packet latency through scheduling. We ask the question: Can a switch with combined input and output queueing be designed to behave identically to an output-queued switch? In this paper, we prove that if the switch uses virtual output queueing and has an internal speedup of just four, it is possible for it to behave identically to an output-queued switch, regardless of the nature of the arriving traffic. Our proof is based on a novel scheduling algorithm, called Most Urgent Cell First. We find that with a speedup of four the most urgent cell first algorithm (or MUCFA) enables perfect emulation of a FIFO output-queued switch, i.e. one in which packets depart in the same order that they arrived. We extend this result to show that with a small modification, the MUCFA algorithm enables perfect emulation of a variety of output scheduling policies, including strict priorities and weighted fair-queueing. This result makes possible switches that perform as if they were output-queued, yet use memories that run more slowly.