A DRAM/SRAM Memory Scheme for Fast Packet Buffers

Authors:
Jorge Garcia-Vidal;Maribel March;Llorenc Cerda;Jesus Corbal;Mateo Valero
Affiliations:
IEEE;-;IEEE;-;IEEE
Venue:
IEEE Transactions on Computers
Year:
2006

Citing 17
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Abstract

We address the design of high-speed packet buffers for Internet routers. We use a general DRAM/SRAM architecture for which previous proposals can be seen as particular cases. For this architecture, large SRAMs are needed to sustain high line rates and a large number of interfaces. A novel algorithm for DRAM bank allocation is presented that reduces the SRAM size requirements of previously proposed schemes by almost an order of magnitude, without having memory fragmentation problems. A technological evaluation shows that our design can support thousands of queues for line rates up to 160 Gbps.