Prefetching in a texture cache architecture
HWWS '98 Proceedings of the ACM SIGGRAPH/EUROGRAPHICS workshop on Graphics hardware
Hardware-software trade-offs in a direct Rambus implementation of the RAMpage memory hierarchy
Proceedings of the eighth international conference on Architectural support for programming languages and operating systems
A performance comparison of contemporary DRAM architectures
ISCA '99 Proceedings of the 26th annual international symposium on Computer architecture
Adding a vector unit to a superscalar processor
ICS '99 Proceedings of the 13th international conference on Supercomputing
Dynamic 3D graphics workload characterization and the architectural implications
Proceedings of the 32nd annual ACM/IEEE international symposium on Microarchitecture
Proceedings of the 27th annual international symposium on Computer architecture
Dynamic Access Ordering for Streamed Computations
IEEE Transactions on Computers
High-Performance DRAMs in Workstation Environments
IEEE Transactions on Computers
Designing a Modern Memory Hierarchy with Hardware Prefetching
IEEE Transactions on Computers
Ray Casting Architectures for Volume Visualization
IEEE Transactions on Visualization and Computer Graphics
Two High-Bandwidth Memory Bus Structures
IEEE Design & Test
A 64Mbit Mesochronous Hybrid Wave Pipelined Multibank DRAM Macro
IMS '00 Revised Papers from the Second International Workshop on Intelligent Memory Systems
Configurable parallel memory architecture for multimedia computers
Journal of Systems Architecture: the EUROMICRO Journal
Overcoming the limitations of conventional vector processors
Proceedings of the 30th annual international symposium on Computer architecture
Design and Implementation of High-Performance Memory Systems for Future Packet Buffers
Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
Reflections on the memory wall
Proceedings of the 1st conference on Computing frontiers
SAGE: an automatic analyzing system for a new high-performance SoC architecture-processor-in-memory
Journal of Systems Architecture: the EUROMICRO Journal
A DRAM/SRAM Memory Scheme for Fast Packet Buffers
IEEE Transactions on Computers
Virtually Pipelined Network Memory
Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture
Languages and Compilers for Parallel Computing
High-bandwidth network memory system through virtual pipelines
IEEE/ACM Transactions on Networking (TON)
Toward to utilize the heterogeneous multiple processors of the chip multiprocessor architecture
EUC'07 Proceedings of the 2007 international conference on Embedded and ubiquitous computing
MemScale: active low-power modes for main memory
Proceedings of the sixteenth international conference on Architectural support for programming languages and operating systems
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Conventional DRAM architectures have reached their practical upper limit in operating frequency and bus width. Scaling the SDRAM's memory clock from 66MHz to 100MHz operation creates numerous system design issues, but only offers 33% additional peak bandwidth. Direct Rambus(tm) DRAMs (RDRAM(r)) provide 1.6Gigabytes/sec (GB/s) bandwidth from a single DRAM approaching 95% efficiency when subjected to typical multimedia PC main memory workloads. Using a 16-bit data field and a separate 8-bit address and control field, the Direct RDRAM has independent control and scheduling of all row and column resources as well as I/O data. Based on conventional printed circuit board (PCB) and connector technology, Direct RDRAM modules fit seamlessly into the existing mechanical space and airflow environment of the industry standard PC chassis while providing 3x the memory bandwidth of the industry-standard 66MHz SDRAM subsystem. Direct RDRAMs have both high speed and low power operating modes serving the needs of both line-operated and portable products.