Two High-Bandwidth Memory Bus Structures

Authors:
Bruce Millar;Peter Gillingham
Affiliations:
-;-
Venue:
IEEE Design & Test
Year:
1999

Citing 2
Cited 1

Direct Rambus Technology: The New Main Memory Standard

IEEE Micro
SLDRAM: High-Performance, Open-Standard Memory

IEEE Micro

Configurable parallel memory architecture for multimedia computers

Journal of Systems Architecture: the EUROMICRO Journal

Quantified Score

Hi-index	0.00

Visualization

Abstract

Two approaches for next generation memory bus architecture, SLDRAM and Direct Rambus, are evaluated using a commercial analog circuit simulator to model transmission line behavior. Sources of error that degrade signal integrity, such as pulse amplitude attenuation, pulse width dependent skew or intersymbol interference, crosstalk, and clock to data skew are quantified to determine the operating margin of the two alternatives. Bus power dissipation is also considered. A fully loaded SLDRAM configuration is shown to have more timing margin than Direct Rambus.