Dynamic 3D graphics workload characterization and the architectural implications
Proceedings of the 32nd annual ACM/IEEE international symposium on Microarchitecture
Two High-Bandwidth Memory Bus Structures
IEEE Design & Test
Trends in Semiconductor Memories
IEEE Micro
An SDRAM Interface for Simplified "At-Speed" Testing of the SLDRAM Internal Array
MTDT '98 Proceedings of the 1998 IEEE International Workshop on Memory Technology, Design and Testing
A DLL design for testing I/O setup and hold times
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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The primary objective of DRAM (Dynamic Random Access Memory) is to offer the largest memory capacity at the lowest possible cost. This is achieved by two means; First, by optimizing the process and the design to minimize die area and second, ensuring that the device can serve high volume markets and can be manufactured in the highest possible volume to achieve the greatest economies of scale. SLDRAM (Synchronous Link DRAM) is a new DRAM interface standard meeting the high data bandwidth requirements of emerging processor architectures. SLDRAM retains the low cost advantages of earlier DRAM interface standards and is therefore destined to become the mainstream commodity memory in the 21st century.